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RegFieldDesc: update DescribedReg to suppot new features

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Megan Wachs
2018-03-09 11:47:03 -08:00
parent 2f239f2a9a
commit 3063fd1b46
1 changed files with 10 additions and 2 deletions
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12
src/main/scala/regmapper/DescribedReg.scala
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@@ -8,6 +8,8 @@ import freechips.rocketchip.util.{AsyncResetRegVec, SimpleRegIO}
object DescribedReg { object DescribedReg {
import freechips.rocketchip.regmapper.RegFieldAccessType._ import freechips.rocketchip.regmapper.RegFieldAccessType._
import freechips.rocketchip.regmapper.RegFieldWrType._
import freechips.rocketchip.regmapper.RegFieldRdAction._
def apply[T <: Data]( def apply[T <: Data](
gen: => T, gen: => T,
@@ -15,9 +17,12 @@ object DescribedReg {
desc: String, desc: String,
reset: Option[T], reset: Option[T],
access: RegFieldAccessType = RW, access: RegFieldAccessType = RW,
wrType: Option[RegFieldWrType] = None,
rdAction: Option[RegFieldRdAction] = None,
volatile: Boolean = false,
enumerations: Map[BigInt, (String, String)] = Map()): (T, RegFieldDesc) = { enumerations: Map[BigInt, (String, String)] = Map()): (T, RegFieldDesc) = {
val rdesc = RegFieldDesc(name, desc, None, None, val rdesc = RegFieldDesc(name, desc, None, None,
access, reset.map{_.litValue}, enumerations) access, wrType, rdAction, volatile, reset.map{_.litValue}, enumerations)
val reg = reset.map{i => RegInit(i)}.getOrElse(Reg(gen)) val reg = reset.map{i => RegInit(i)}.getOrElse(Reg(gen))
reg.suggestName(name + "_reg") reg.suggestName(name + "_reg")
(reg, rdesc) (reg, rdesc)
@@ -29,9 +34,12 @@ object DescribedReg {
desc: String, desc: String,
reset: Int, reset: Int,
access: RegFieldAccessType = RW, access: RegFieldAccessType = RW,
wrType: Option[RegFieldWrType] = None,
rdAction: Option[RegFieldRdAction] = None,
volatile: Boolean = false,
enumerations: Map[BigInt, (String, String)] = Map()): (SimpleRegIO, RegFieldDesc) = { enumerations: Map[BigInt, (String, String)] = Map()): (SimpleRegIO, RegFieldDesc) = {
val rdesc = RegFieldDesc(name, desc, None, None, val rdesc = RegFieldDesc(name, desc, None, None,
access, Some(reset), enumerations) access, wrType, rdAction, volatile, Some(reset), enumerations)
val reg = Module(new AsyncResetRegVec(w = width, init = reset)) val reg = Module(new AsyncResetRegVec(w = width, init = reset))
reg.suggestName(name + "_reg") reg.suggestName(name + "_reg")
(reg.io, rdesc) (reg.io, rdesc)