send DMA requests through MMIO and get responses through CSRs
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@ -193,3 +193,27 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
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state := s_ready
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}
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}
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class DecoupledTLB(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val req = Decoupled(new TLBReq).flip
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val resp = Decoupled(new TLBResp)
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val ptw = new TLBPTWIO
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}
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val reqq = Queue(io.req)
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val tlb = Module(new TLB)
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val resp_helper = DecoupledHelper(
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reqq.valid, tlb.io.req.ready, io.resp.ready)
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val tlb_miss = tlb.io.resp.miss
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tlb.io.req.valid := resp_helper.fire(tlb.io.req.ready)
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tlb.io.req.bits := reqq.bits
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reqq.ready := resp_helper.fire(reqq.valid, !tlb_miss)
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io.resp.valid := resp_helper.fire(io.resp.ready, !tlb_miss)
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io.resp.bits := tlb.io.resp
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io.ptw <> tlb.io.ptw
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}
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