riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

send DMA requests through MMIO and get responses through CSRs

Browse Source
This commit is contained in:
Howard Mao
2016-01-14 11:37:58 -08:00
parent 58fcc6b7c6
commit 305185c034
7 changed files with 189 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
rocket/src/main/scala/csr.scala
View File

@ -252,12 +252,16 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}
for (i <- 0 until nCustomMrwCsrs) {
val addr = 0x790 + i // turn 0x790 into parameter CustomMRWCSRBase?
require(addr >= 0x780 && addr <= 0x7ff, "custom MRW CSR address " + i + " is out of range")
val addr = CSRs.mrwbase + i
require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
read_mapping += addr -> io.custom_mrw_csrs(i)
}
for ((addr, i) <- roccCsrs.zipWithIndex) {
require(!read_mapping.contains(addr), "RoCC: CSR address " + addr + " is already in use")
read_mapping += addr -> io.rocc.csr.rdata(i)
}
val addr = Mux(cpu_ren, io.rw.addr, host_csr_bits.addr)
val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) }
@ -449,6 +453,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}
}
io.rocc.csr.waddr := addr
io.rocc.csr.wdata := wdata
io.rocc.csr.wen := wen
when(this.reset) {
reg_mstatus.zero1 := 0
reg_mstatus.zero2 := 0