Implement client-side DMA controller
This commit is contained in:
Howard Mao
parent
01a3447989
commit
304d8b814a
337
rocket/src/main/scala/dma.scala
Normal file
337
rocket/src/main/scala/dma.scala
Normal file
@ -0,0 +1,337 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.DmaRequest._
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import junctions.ParameterizedBundle
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import cde.Parameters
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trait HasClientDmaParameters extends HasCoreParameters with HasDmaParameters {
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val dmaAddrBits = coreMaxAddrBits
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val dmaSizeBits = coreMaxAddrBits
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val dmaSegmentBits = 24
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}
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abstract class ClientDmaBundle(implicit val p: Parameters)
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extends ParameterizedBundle()(p) with HasClientDmaParameters
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abstract class ClientDmaModule(implicit val p: Parameters)
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extends Module with HasClientDmaParameters
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class ClientDmaRequest(implicit p: Parameters) extends ClientDmaBundle()(p) {
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val cmd = UInt(width = DMA_CMD_SZ)
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val src_start = UInt(width = dmaAddrBits)
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val dst_start = UInt(width = dmaAddrBits)
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val src_stride = UInt(width = dmaSizeBits)
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val dst_stride = UInt(width = dmaSizeBits)
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val segment_size = UInt(width = dmaSizeBits)
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val nsegments = UInt(width = dmaSegmentBits)
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}
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object ClientDmaRequest {
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def apply(cmd: UInt,
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src_start: UInt,
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dst_start: UInt,
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segment_size: UInt,
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nsegments: UInt = UInt(1),
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src_stride: UInt = UInt(0),
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dst_stride: UInt = UInt(0))
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(implicit p: Parameters) = {
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val req = Wire(new ClientDmaRequest)
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req.cmd := cmd
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req.src_start := src_start
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req.dst_start := dst_start
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req.src_stride := src_stride
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req.dst_stride := dst_stride
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req.segment_size := segment_size
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req.nsegments := nsegments
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req
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}
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}
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object ClientDmaResponse {
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val pagefault = UInt("b01")
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val outer_err = UInt("b10")
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def apply(status: UInt = UInt(0))(implicit p: Parameters) = {
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val resp = Wire(new ClientDmaResponse)
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resp.status := status
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resp
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}
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}
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class ClientDmaResponse(implicit p: Parameters) extends ClientDmaBundle {
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val status = UInt(width = dmaStatusBits)
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}
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class ClientDmaIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val req = Decoupled(new ClientDmaRequest)
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val resp = Valid(new ClientDmaResponse).flip
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}
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class DmaFrontend(implicit val p: Parameters)
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extends Module with HasClientDmaParameters {
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val io = new Bundle {
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val cpu = (new ClientDmaIO).flip
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val dma = new DmaIO
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val ptw = new TLBPTWIO
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val busy = Bool(OUTPUT)
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}
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private val pgSize = 1 << pgIdxBits
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val priv = Mux(io.ptw.status.mprv, io.ptw.status.prv1, io.ptw.status.prv)
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val vm_enabled = io.ptw.status.vm(3) && priv <= UInt(PRV_S)
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val cmd = Reg(UInt(width = DMA_CMD_SZ))
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val segment_size = Reg(UInt(width = dmaSizeBits))
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val bytes_left = Reg(UInt(width = dmaSizeBits))
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val segments_left = Reg(UInt(width = dmaSegmentBits))
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val src_vaddr = Reg(UInt(width = dmaAddrBits))
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val dst_vaddr = Reg(UInt(width = dmaAddrBits))
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val src_vpn = src_vaddr(dmaAddrBits - 1, pgIdxBits)
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val dst_vpn = dst_vaddr(dmaAddrBits - 1, pgIdxBits)
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val src_idx = src_vaddr(pgIdxBits - 1, 0)
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val dst_idx = dst_vaddr(pgIdxBits - 1, 0)
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val src_pglen = UInt(pgSize) - src_idx
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val dst_pglen = UInt(pgSize) - dst_idx
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val src_stride = Reg(UInt(width = dmaSizeBits))
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val dst_stride = Reg(UInt(width = dmaSizeBits))
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val src_ppn = Reg(UInt(width = ppnBits))
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val dst_ppn = Reg(UInt(width = ppnBits))
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val src_paddr = Mux(vm_enabled, Cat(src_ppn, src_idx), src_vaddr)
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val dst_paddr = Mux(vm_enabled, Cat(dst_ppn, dst_idx), dst_vaddr)
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val last_src_vpn = Reg(UInt(width = vpnBits))
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val last_dst_vpn = Reg(UInt(width = vpnBits))
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val tx_len = Mux(!vm_enabled, bytes_left,
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Util.minUInt(src_pglen, dst_pglen, bytes_left))
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val (dma_xact_id, _) = Counter(io.dma.req.fire(), nDmaXactsPerClient)
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val dma_busy = Reg(init = UInt(0, nDmaXactsPerClient))
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val (s_idle :: s_translate :: s_dma_req :: s_dma_update ::
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s_prepare :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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// lower bit is for src, higher bit is for dst
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val to_translate = Reg(init = UInt(0, 2))
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val ptw_sent = Reg(init = UInt(0, 2))
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val ptw_to_send = to_translate & ~ptw_sent
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val ptw_resp_id = Reg(init = UInt(0, 1))
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val resp_status = Reg(UInt(width = dmaStatusBits))
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io.ptw.req.valid := ptw_to_send.orR && vm_enabled
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io.ptw.req.bits.addr := Mux(ptw_to_send(0), src_vpn, dst_vpn)
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io.ptw.req.bits.prv := io.ptw.status.prv
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io.ptw.req.bits.store := !ptw_to_send(0) // storing to destination
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io.ptw.req.bits.fetch := Bool(true)
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when (io.ptw.req.fire()) {
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ptw_sent := ptw_sent | PriorityEncoderOH(ptw_to_send)
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}
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when (io.ptw.resp.valid) {
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when (io.ptw.resp.bits.error) {
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resp_status := ClientDmaResponse.pagefault
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state := s_finish
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}
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val recv_choice = PriorityEncoderOH(to_translate)
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to_translate := to_translate & ~recv_choice
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// getting the src translation
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// if this is a prefetch, dst_ppn and src_ppn should be equal
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when (recv_choice(0) || cmd(1)) {
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src_ppn := io.ptw.resp.bits.pte.ppn
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} .otherwise {
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dst_ppn := io.ptw.resp.bits.pte.ppn
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}
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}
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io.cpu.req.ready := state === s_idle
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io.cpu.resp.valid := state === s_finish
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io.cpu.resp.bits := ClientDmaResponse(resp_status)
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io.dma.req.valid := state === s_dma_req && !dma_busy(dma_xact_id)
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io.dma.req.bits := DmaRequest(
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client_xact_id = dma_xact_id,
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cmd = cmd,
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source = src_paddr,
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dest = dst_paddr,
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length = tx_len)
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io.dma.resp.ready := Bool(true)
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when (io.cpu.req.fire()) {
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val req = io.cpu.req.bits
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cmd := req.cmd
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src_vaddr := req.src_start
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dst_vaddr := req.dst_start
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src_stride := req.src_stride
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dst_stride := req.dst_stride
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segment_size := req.segment_size
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segments_left := req.nsegments - UInt(1)
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bytes_left := req.segment_size
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to_translate := Mux(req.cmd(1), UInt("b10"), UInt("b11"))
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ptw_sent := UInt(0)
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state := Mux(vm_enabled, s_translate, s_dma_req)
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}
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when (state === s_translate && !to_translate.orR) {
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state := s_dma_req
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}
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when (io.dma.req.fire()) {
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src_vaddr := src_vaddr + tx_len
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dst_vaddr := dst_vaddr + tx_len
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bytes_left := bytes_left - tx_len
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dma_busy := dma_busy | UIntToOH(dma_xact_id)
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state := s_dma_update
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}
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when (io.dma.resp.fire()) {
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dma_busy := dma_busy & ~UIntToOH(io.dma.resp.bits.client_xact_id)
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}
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when (state === s_dma_update) {
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when (bytes_left === UInt(0)) {
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when (segments_left === UInt(0)) {
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resp_status := UInt(0)
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state := s_finish
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} .otherwise {
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last_src_vpn := src_vpn
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last_dst_vpn := dst_vpn
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src_vaddr := src_vaddr + src_stride
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dst_vaddr := dst_vaddr + dst_stride
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bytes_left := segment_size
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segments_left := segments_left - UInt(1)
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state := Mux(vm_enabled, s_prepare, s_dma_req)
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}
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} .otherwise {
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to_translate := Cat(dst_idx === UInt(0), !cmd(1) && src_idx === UInt(0))
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ptw_sent := UInt(0)
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state := s_translate
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}
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}
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when (state === s_prepare) {
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to_translate := Cat(
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dst_vpn =/= last_dst_vpn,
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src_vpn =/= last_src_vpn && !cmd(1))
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ptw_sent := UInt(0)
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state := s_translate
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}
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when (state === s_finish) { state := s_idle }
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io.busy := (state =/= s_idle) || dma_busy.orR
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}
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object DmaCtrlRegNumbers {
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val SRC_STRIDE = 0
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val DST_STRIDE = 1
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val SEGMENT_SIZE = 2
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val NSEGMENTS = 3
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val RESP_STATUS = 4
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}
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import DmaCtrlRegNumbers._
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class DmaCtrlRegFile(implicit p: Parameters) extends ClientDmaModule()(p) {
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private val nWriteRegs = 4
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private val nReadRegs = 1
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private val nRegs = nWriteRegs + nReadRegs
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val io = new Bundle {
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val wen = Bool(INPUT)
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val addr = UInt(INPUT, log2Up(nRegs))
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val wdata = UInt(INPUT, dmaSizeBits)
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val rdata = UInt(OUTPUT, dmaSizeBits)
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val src_stride = UInt(OUTPUT, dmaSizeBits)
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val dst_stride = UInt(OUTPUT, dmaSizeBits)
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val segment_size = UInt(OUTPUT, dmaSizeBits)
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val nsegments = UInt(OUTPUT, dmaSegmentBits)
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val status = UInt(INPUT, dmaStatusBits)
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}
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val regs = Reg(Vec(nWriteRegs, UInt(width = dmaSizeBits)))
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io.src_stride := regs(SRC_STRIDE)
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io.dst_stride := regs(DST_STRIDE)
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io.segment_size := regs(SEGMENT_SIZE)
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io.nsegments := regs(NSEGMENTS)
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when (io.wen && io.addr < UInt(nWriteRegs)) {
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regs.write(io.addr, io.wdata)
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}
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io.rdata := MuxLookup(io.addr, regs(io.addr), Seq(
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UInt(RESP_STATUS) -> io.status))
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}
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class DmaController(implicit p: Parameters) extends RoCC()(p)
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with HasClientDmaParameters {
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io.mem.req.valid := Bool(false)
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io.autl.acquire.valid := Bool(false)
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io.autl.grant.ready := Bool(false)
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io.iptw.req.valid := Bool(false)
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io.pptw.req.valid := Bool(false)
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val cmd = Queue(io.cmd)
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val inst = cmd.bits.inst
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val is_transfer = inst.funct < UInt(4)
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val is_cr_write = inst.funct === UInt(4)
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val is_cr_read = inst.funct === UInt(5)
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val is_cr_access = is_cr_write || is_cr_read
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val resp_rd = Reg(io.resp.bits.rd)
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val resp_data = Reg(io.resp.bits.data)
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val s_idle :: s_resp :: Nil = Enum(Bits(), 2)
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val state = Reg(init = s_idle)
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val reg_status = Reg(UInt(width = dmaStatusBits))
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val crfile = Module(new DmaCtrlRegFile)
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crfile.io.addr := cmd.bits.rs1
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crfile.io.wdata := cmd.bits.rs2
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crfile.io.wen := cmd.fire() && is_cr_write
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val frontend = Module(new DmaFrontend)
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io.dma <> frontend.io.dma
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io.dptw <> frontend.io.ptw
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frontend.io.cpu.req.valid := cmd.valid && is_transfer
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frontend.io.cpu.req.bits := ClientDmaRequest(
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cmd = cmd.bits.inst.funct,
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src_start = cmd.bits.rs2,
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dst_start = cmd.bits.rs1,
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src_stride = crfile.io.src_stride,
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dst_stride = crfile.io.dst_stride,
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segment_size = crfile.io.segment_size,
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nsegments = crfile.io.nsegments)
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cmd.ready := state === s_idle && (!is_transfer || frontend.io.cpu.req.ready)
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io.resp.valid := state === s_resp
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io.resp.bits.rd := resp_rd
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io.resp.bits.data := resp_data
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when (cmd.fire()) {
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when (is_cr_read) {
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resp_rd := inst.rd
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resp_data := crfile.io.rdata
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state := s_resp
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}
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}
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when (io.resp.fire()) { state := s_idle }
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when (frontend.io.cpu.resp.valid) {
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reg_status := frontend.io.cpu.resp.bits.status
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}
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io.busy := (state =/= s_idle) || cmd.valid || frontend.io.busy
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io.interrupt := Bool(false)
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}
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@ -50,6 +50,8 @@ class RoCCInterface(implicit p: Parameters) extends Bundle {
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val fpu_req = Decoupled(new FPInput)
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val fpu_resp = Decoupled(new FPResult).flip
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val exception = Bool(INPUT)
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val dma = new DmaIO
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}
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abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
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@ -14,7 +14,8 @@ case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 0,
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useFPU: Boolean = false)
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useFPU: Boolean = false,
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useDma: Boolean = false)
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abstract class Tile(resetSignal: Bool = null)
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(implicit p: Parameters) extends Module(_reset = resetSignal) {
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@ -22,6 +23,7 @@ abstract class Tile(resetSignal: Bool = null)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val nDmaPorts = buildRocc.filter(_.useDma).size
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val nDCachePorts = 2 + nRocc
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val nPTWPorts = 2 + 3 * nRocc
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val nCachedTileLinkPorts = 1
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@ -31,6 +33,7 @@ abstract class Tile(resetSignal: Bool = null)
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val host = new HtifIO
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val dma = new DmaIO
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}
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}
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@ -104,6 +107,14 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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}
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}
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if (nDmaPorts > 0) {
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val dmaArb = Module(new DmaArbiter(nDmaPorts))
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dmaArb.io.in <> roccs.zip(buildRocc)
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.filter { case (_, params) => params.useDma }
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.map { case (rocc, _) => rocc.io.dma }
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io.dma <> dmaArb.io.out
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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@ -117,4 +128,9 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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if (!usingRocc || nDmaPorts == 0) {
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io.dma.req.valid := Bool(false)
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io.dma.resp.ready := Bool(false)
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}
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}
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@ -21,6 +21,12 @@ object Util {
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implicit def booleanToIntConv(x: Boolean) = new AnyRef {
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def toInt: Int = if (x) 1 else 0
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}
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def minUInt(values: Seq[UInt]): UInt =
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values.reduce((a, b) => Mux(a < b, a, b))
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def minUInt(first: UInt, rest: UInt*): UInt =
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minUInt(first +: rest.toSeq)
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}
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import Util._
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