riscv/rocket-chip
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bypass stores to subsequent loads

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since we handle subword stores as RMW operations, this occurs frequently
This commit is contained in:
Andrew Waterman
2012-11-20 01:32:33 -08:00
parent 395e4e3dd6
commit 30038bda8a
2 changed files with 97 additions and 97 deletions
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2
rocket/src/main/scala/core.scala
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@ -110,7 +110,7 @@ class Core(implicit conf: RocketConfiguration) extends Component
vu.io.xcpt.hold := ctrl.io.vec_iface.hold
// hooking up vector memory interface
dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data)
dmem(2).req.bits.data := RegEn(StoreGen(vu.io.dmem_req.bits).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
dmem(2).req <> vu.io.dmem_req
dmem(2).resp <> vu.io.dmem_resp