riscv/rocket-chip
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remove datapath register resets resets

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This commit is contained in:
Andrew Waterman 2012-01-01 16:09:40 -08:00
parent f9160c53cf
commit 2f8fcebea0
6 changed files with 58 additions and 59 deletions
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18
rocket/src/main/scala/divider.scala
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@ -41,16 +41,16 @@ class rocketDivider(width : Int) extends Component {
val state = Reg(resetVal = s_ready); val state = Reg(resetVal = s_ready);
val count_bits = java.math.BigInteger.valueOf(width).bitLength(); val count_bits = java.math.BigInteger.valueOf(width).bitLength();
val count = Reg(resetVal = UFix(0, count_bits)); val count = Reg() { UFix() };
val divby0 = Reg(resetVal = Bool(false)); val divby0 = Reg() { Bool() };
val neg_quo = Reg(resetVal = Bool(false)); val neg_quo = Reg() { Bool() };
val neg_rem = Reg(resetVal = Bool(false)); val neg_rem = Reg() { Bool() };
val reg_waddr = Reg(resetVal = UFix(0, 5)); val reg_waddr = Reg() { UFix() };
val rem = Reg(resetVal = Bool(false)); val rem = Reg() { Bool() };
val half = Reg(resetVal = Bool(false)); val half = Reg() { Bool() };
val divisor = Reg(resetVal = UFix(0, width)); val divisor = Reg() { UFix() };
val remainder = Reg(resetVal = UFix(0, 2*width+1)); val remainder = Reg() { UFix() };
val subtractor = remainder(2*width, width).toUFix - divisor; val subtractor = remainder(2*width, width).toUFix - divisor;
val tc = (io.div_fn === DIV_D) || (io.div_fn === DIV_R); val tc = (io.div_fn === DIV_D) || (io.div_fn === DIV_R);

53
rocket/src/main/scala/dpath.scala
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@ -66,31 +66,31 @@ class rocketDpath extends Component
// instruction decode definitions // instruction decode definitions
val id_reg_valid = Reg(resetVal = Bool(false)); val id_reg_valid = Reg(resetVal = Bool(false));
val id_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS));
val id_reg_pc_plus4 = Reg(resetVal = UFix(0,VADDR_BITS));
val id_reg_inst = Reg(resetVal = NOP); val id_reg_inst = Reg(resetVal = NOP);
val id_reg_pc = Reg() { UFix() };
val id_reg_pc_plus4 = Reg() { UFix() };
// execute definitions // execute definitions
val ex_reg_valid = Reg(resetVal = Bool(false)); val ex_reg_valid = Reg(resetVal = Bool(false));
val ex_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS)); val ex_reg_pc = Reg() { UFix() };
val ex_reg_pc_plus4 = Reg(resetVal = UFix(0,VADDR_BITS)); val ex_reg_pc_plus4 = Reg() { UFix() };
val ex_reg_inst = Reg(resetVal = Bits(0,32)); val ex_reg_inst = Reg() { Bits() };
val ex_reg_raddr2 = Reg(resetVal = UFix(0,5)); val ex_reg_raddr2 = Reg() { UFix() };
val ex_reg_raddr1 = Reg(resetVal = UFix(0,5)); val ex_reg_raddr1 = Reg() { UFix() };
val ex_reg_rs2 = Reg(resetVal = Bits(0,64)); val ex_reg_rs2 = Reg() { Bits() };
val ex_reg_rs1 = Reg(resetVal = Bits(0,64)); val ex_reg_rs1 = Reg() { Bits() };
val ex_reg_waddr = Reg(resetVal = UFix(0,5)); val ex_reg_waddr = Reg() { UFix() };
val ex_reg_ctrl_sel_alu2 = Reg(resetVal = A2_X); val ex_reg_ctrl_sel_alu2 = Reg() { UFix() };
val ex_reg_ctrl_sel_alu1 = Reg(resetVal = A1_X); val ex_reg_ctrl_sel_alu1 = Reg() { UFix() };
val ex_reg_ctrl_eret = Reg(resetVal = Bool(false)); val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
val ex_reg_ctrl_fn_dw = Reg(resetVal = DW_X); val ex_reg_ctrl_fn_dw = Reg() { UFix() };
val ex_reg_ctrl_fn_alu = Reg(resetVal = FN_X); val ex_reg_ctrl_fn_alu = Reg() { UFix() };
val ex_reg_ctrl_ll_wb = Reg(resetVal = Bool(false)); val ex_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val ex_reg_ctrl_mul_val = Reg(resetVal = Bool(false)); val ex_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
val ex_reg_ctrl_mul_fn = Reg(resetVal = MUL_X); val ex_reg_ctrl_mul_fn = Reg() { UFix() };
val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false)); val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val ex_reg_ctrl_div_fn = Reg(resetVal = DIV_X); val ex_reg_ctrl_div_fn = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg(resetVal = WB_X); val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_reg_ctrl_wen = Reg(resetVal = Bool(false)); val ex_reg_ctrl_wen = Reg(resetVal = Bool(false));
val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false)); val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false)); val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
@ -98,22 +98,22 @@ class rocketDpath extends Component
// memory definitions // memory definitions
val mem_reg_valid = Reg(resetVal = Bool(false)); val mem_reg_valid = Reg(resetVal = Bool(false));
val mem_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS)); val mem_reg_pc = Reg() { UFix() };
val mem_reg_waddr = Reg(resetVal = UFix(0,5)); val mem_reg_waddr = Reg() { UFix() };
val mem_reg_wdata = Reg(resetVal = Bits(0,64)); val mem_reg_wdata = Reg() { Bits() };
val mem_reg_raddr2 = Reg(resetVal = UFix(0,5)); val mem_reg_raddr2 = Reg() { UFix() };
val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false)); val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen = Reg(resetVal = Bool(false)); val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false)); val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
// writeback definitions // writeback definitions
val wb_reg_waddr = Reg(resetVal = UFix(0,5)); val wb_reg_waddr = Reg() { UFix() };
val wb_reg_wdata = Reg(resetVal = Bits(0,64)); val wb_reg_wdata = Reg() { Bits() };
val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false)); val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen = Reg(resetVal = Bool(false)); val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
val r_dmem_resp_val = Reg(resetVal = Bool(false)); val r_dmem_resp_val = Reg(resetVal = Bool(false));
val r_dmem_resp_waddr = Reg(resetVal = UFix(0,5)); val r_dmem_resp_waddr = Reg() { UFix() };
// instruction fetch stage // instruction fetch stage
val if_pc_plus4 = if_reg_pc + UFix(4); val if_pc_plus4 = if_reg_pc + UFix(4);
@ -123,10 +123,9 @@ class rocketDpath extends Component
val ex_sign_extend_split = val ex_sign_extend_split =
Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10)); Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
// FIXME: which bits to extract should be calculated based on VADDR_BITS
val branch_adder_rhs = val branch_adder_rhs =
Mux(io.ctrl.ex_jmp, Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0,1)), Mux(io.ctrl.ex_jmp, Cat(Fill(VADDR_BITS-26, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0,1)),
Cat(ex_sign_extend_split(41,0), UFix(0, 1))); Cat(ex_sign_extend_split(VADDR_BITS-2,0), UFix(0, 1)));
val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix; val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;

18
rocket/src/main/scala/dpath_util.scala
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@ -65,17 +65,17 @@ class rocketDpathPCR extends Component
{ {
val io = new ioDpathPCR(); val io = new ioDpathPCR();
val reg_epc = Reg(resetVal = UFix(0, VADDR_BITS)); val reg_epc = Reg() { UFix() };
val reg_badvaddr = Reg(resetVal = UFix(0, VADDR_BITS)); val reg_badvaddr = Reg() { UFix() };
val reg_ebase = Reg(resetVal = UFix(0, VADDR_BITS)); val reg_ebase = Reg() { UFix() };
val reg_count = Reg(resetVal = UFix(0, 32)); val reg_count = Reg() { UFix() };
val reg_compare = Reg(resetVal = UFix(0, 32)); val reg_compare = Reg() { UFix() };
val reg_cause = Reg(resetVal = Bits(0, 5)); val reg_cause = Reg() { Bits() };
val reg_tohost = Reg(resetVal = Bits(0, 32)); val reg_tohost = Reg(resetVal = Bits(0, 32));
val reg_fromhost = Reg(resetVal = Bits(0, 32)); val reg_fromhost = Reg(resetVal = Bits(0, 32));
val reg_k0 = Reg(resetVal = Bits(0, 64)); val reg_k0 = Reg() { Bits() };
val reg_k1 = Reg(resetVal = Bits(0, 64)); val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg(resetVal = UFix(0, PADDR_BITS)); val reg_ptbr = Reg() { UFix() };
val reg_error_mode = Reg(resetVal = Bool(false)); val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false)); val reg_status_vm = Reg(resetVal = Bool(false));

10
rocket/src/main/scala/dtlb.scala
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@ -42,12 +42,12 @@ class rocketDTLB(entries: Int) extends Component
val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() }; val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() };
val state = Reg(resetVal = s_ready); val state = Reg(resetVal = s_ready);
val r_cpu_req_vpn = Reg(resetVal = Bits(0, VPN_BITS));
val r_cpu_req_val = Reg(resetVal = Bool(false)); val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_cpu_req_cmd = Reg(resetVal = Bits(0,4)); val r_cpu_req_vpn = Reg() { Bits() }
val r_cpu_req_asid = Reg(resetVal = Bits(0,ASID_BITS)); val r_cpu_req_cmd = Reg() { Bits() }
val r_refill_tag = Reg(resetVal = Bits(0,ASID_BITS+VPN_BITS)); val r_cpu_req_asid = Reg() { Bits() }
val r_refill_waddr = Reg(resetVal = UFix(0,addr_bits)); val r_refill_tag = Reg() { Bits() }
val r_refill_waddr = Reg() { UFix() }
val repl_count = Reg(resetVal = UFix(0,addr_bits)); val repl_count = Reg(resetVal = UFix(0,addr_bits));
when (io.cpu.req_val && io.cpu.req_rdy) { when (io.cpu.req_val && io.cpu.req_rdy) {

8
rocket/src/main/scala/itlb.scala
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@ -96,11 +96,11 @@ class rocketITLB(entries: Int) extends Component
val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() }; val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() };
val state = Reg(resetVal = s_ready); val state = Reg(resetVal = s_ready);
val r_cpu_req_vpn = Reg(resetVal = Bits(0, VPN_BITS));
val r_cpu_req_val = Reg(resetVal = Bool(false)); val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_cpu_req_asid = Reg(resetVal = Bits(0,ASID_BITS)); val r_cpu_req_vpn = Reg() { Bits() };
val r_refill_tag = Reg(resetVal = Bits(0, ASID_BITS+VPN_BITS)); val r_cpu_req_asid = Reg() { Bits() };
val r_refill_waddr = Reg(resetVal = UFix(0, addr_bits)); val r_refill_tag = Reg() { Bits() };
val r_refill_waddr = Reg() { UFix() };
val repl_count = Reg(resetVal = UFix(0, addr_bits)); val repl_count = Reg(resetVal = UFix(0, addr_bits));
when (io.cpu.req_val && io.cpu.req_rdy) { when (io.cpu.req_val && io.cpu.req_rdy) {

10
rocket/src/main/scala/ptw.scala
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@ -60,12 +60,12 @@ class rocketPTW extends Component
val s_ready :: s_l1_req :: s_l1_wait :: s_l1_fake :: s_l2_req :: s_l2_wait :: s_l2_fake:: s_l3_req :: s_l3_wait :: s_done :: s_error :: Nil = Enum(11) { UFix() }; val s_ready :: s_l1_req :: s_l1_wait :: s_l1_fake :: s_l2_req :: s_l2_wait :: s_l2_fake:: s_l3_req :: s_l3_wait :: s_done :: s_error :: Nil = Enum(11) { UFix() };
val state = Reg(resetVal = s_ready); val state = Reg(resetVal = s_ready);
val r_req_vpn = Reg(resetVal = Bits(0,VPN_BITS)); val r_req_vpn = Reg() { Bits() }
val r_req_dest = Reg(resetVal = Bool(false)); // 0 = ITLB, 1 = DTLB val r_req_dest = Reg() { Bool() }
val req_addr = Reg(resetVal = UFix(0,PADDR_BITS)); val req_addr = Reg() { UFix() };
val r_resp_ppn = Reg(resetVal = Bits(0,PPN_BITS)); val r_resp_ppn = Reg() { Bits() };
val r_resp_perm = Reg(resetVal = Bits(0,PERM_BITS)); val r_resp_perm = Reg() { Bits() };
val vpn_idx = Mux(state === s_l2_wait, r_req_vpn(9,0), r_req_vpn(19,10)); val vpn_idx = Mux(state === s_l2_wait, r_req_vpn(9,0), r_req_vpn(19,10));
val req_val = io.itlb.req_val || io.dtlb.req_val; val req_val = io.itlb.req_val || io.dtlb.req_val;