riscv/rocket-chip
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remove datapath register resets resets

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This commit is contained in:
Andrew Waterman
2012-01-01 16:09:40 -08:00
parent f9160c53cf
commit 2f8fcebea0
6 changed files with 58 additions and 59 deletions
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10
rocket/src/main/scala/ptw.scala
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@ -60,12 +60,12 @@ class rocketPTW extends Component
val s_ready :: s_l1_req :: s_l1_wait :: s_l1_fake :: s_l2_req :: s_l2_wait :: s_l2_fake:: s_l3_req :: s_l3_wait :: s_done :: s_error :: Nil = Enum(11) { UFix() };
val state = Reg(resetVal = s_ready);
val r_req_vpn = Reg(resetVal = Bits(0,VPN_BITS));
val r_req_dest = Reg(resetVal = Bool(false)); // 0 = ITLB, 1 = DTLB
val r_req_vpn = Reg() { Bits() }
val r_req_dest = Reg() { Bool() }
val req_addr = Reg(resetVal = UFix(0,PADDR_BITS));
val r_resp_ppn = Reg(resetVal = Bits(0,PPN_BITS));
val r_resp_perm = Reg(resetVal = Bits(0,PERM_BITS));
val req_addr = Reg() { UFix() };
val r_resp_ppn = Reg() { Bits() };
val r_resp_perm = Reg() { Bits() };
val vpn_idx = Mux(state === s_l2_wait, r_req_vpn(9,0), r_req_vpn(19,10));
val req_val = io.itlb.req_val || io.dtlb.req_val;