riscv/rocket-chip
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clint: don't ask for what you know (nTiles)

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Wesley W. Terpstra 2017-06-20 17:21:53 -07:00
parent 1c97a2a94c
commit 2f2fe0a973
2 changed files with 3 additions and 2 deletions
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2
src/main/scala/coreplex/RISCVPlatform.scala
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@ -25,7 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
plic.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
plic.intnode := int_xbar.intnode
val clint = LazyModule(new CoreplexLocalInterrupter(nTiles, p(ClintKey)))
val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey)))
clint.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
lazy val dts = DTS(bindingTree)

3
src/main/scala/uncore/devices/Clint.scala
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@ -32,7 +32,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000)
def address = AddressSet(baseAddress, ClintConsts.size-1)
}
class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Parameters) extends LazyModule
class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
{
import ClintConsts._
@ -66,6 +66,7 @@ class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Par
reg := newTime >> i
}
val nTiles = intnode.edgesOut.size
val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }