RegFieldDesc: Add more features to support more IP-XACT like descriptions & emit them in the JSON
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@ -7,7 +7,6 @@ import chisel3.util.{ReadyValidIO}
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import freechips.rocketchip.util.{SimpleRegIO}
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import freechips.rocketchip.util.{SimpleRegIO}
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// This information is not used internally by the regmap(...) function.
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// This information is not used internally by the regmap(...) function.
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// However, the author of a RegField may be the best person to provide this
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// However, the author of a RegField may be the best person to provide this
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// information which is likely to be needed by downstream SW and Documentation
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// information which is likely to be needed by downstream SW and Documentation
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@ -15,26 +14,47 @@ import freechips.rocketchip.util.{SimpleRegIO}
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object RegFieldAccessType extends scala.Enumeration {
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object RegFieldAccessType extends scala.Enumeration {
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type RegFieldAccessType = Value
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type RegFieldAccessType = Value
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val R, W, RW, RSPECIAL, WSPECIAL, RWSPECIAL, OTHER = Value
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val R, W, RW = Value
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}
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}
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import RegFieldAccessType._
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import RegFieldAccessType._
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object RegFieldWrType extends scala.Enumeration {
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type RegFieldWrType = Value
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val ONE_TO_CLEAR, ONE_TO_SET, ONE_TO_TOGGLE, ZERO_TO_CLEAR,
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ZERO_TO_SET, ZERO_TO_TOGGLE, CLEAR, SET, MODIFY = Value
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}
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import RegFieldWrType._
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object RegFieldRdAction extends scala.Enumeration {
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type RegFieldRdAction = Value
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val CLEAR, SET, MODIFY = Value
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}
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import RegFieldRdAction._
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case class RegFieldDesc (
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case class RegFieldDesc (
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name: String,
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name: String,
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desc: String,
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desc: String,
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group: Option[String] = None,
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group: Option[String] = None,
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groupDesc: Option[String] = None,
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groupDesc: Option[String] = None,
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access: RegFieldAccessType = RegFieldAccessType.RW,
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access: RegFieldAccessType = RegFieldAccessType.RW,
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wrType: Option[RegFieldWrType] = None,
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rdAction: Option[RegFieldRdAction] = None,
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volatile: Boolean = false,
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// TODO: testable?
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reset: Option[BigInt] = None,
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reset: Option[BigInt] = None,
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enumerations: Map[BigInt, (String, String)] = Map()
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enumerations: Map[BigInt, (String, String)] = Map()
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){
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){
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}
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}
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// Our descriptions are in terms of RegFields only, which is somewhat unusual for
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object RegFieldDescReserved {
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// developers who are used to things being defined as bitfields within registers.
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def apply(): RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0))
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// The "Group" allows a string & (optional) description to be added which describes the conceptual "Group"
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}
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// the RegField belongs to. This can be used by downstream flows as they see fit to
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// present the information.
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// Our descriptions are in terms of RegFields only, which is somewhat
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// unusual for developers who are used to things being defined as bitfields
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// within registers. The "Group" allows a string & (optional) description
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// to be added which describes the conceptual "Group" the RegField belongs to.
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// This can be used by downstream flows as they see fit to present the information.
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object RegFieldGroup {
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object RegFieldGroup {
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def apply (name: String, desc: Option[String], regs: Seq[RegField], descFirstOnly: Boolean = true): Seq[RegField] = {
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def apply (name: String, desc: Option[String], regs: Seq[RegField], descFirstOnly: Boolean = true): Seq[RegField] = {
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@ -125,8 +145,7 @@ object RegField
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// Byte address => sequence of bitfields, lowest index => lowest address
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// Byte address => sequence of bitfields, lowest index => lowest address
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type Map = (Int, Seq[RegField])
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), (),
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def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDescReserved()))
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Some(RegFieldDesc("reserved", "", access = RegFieldAccessType.R, reset = Some(0))))
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def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
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def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
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def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))
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def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))
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@ -142,7 +161,7 @@ object RegField
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// Setting takes priority over clearing.
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// Setting takes priority over clearing.
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def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField =
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def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField =
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RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }),
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RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }),
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desc.map{_.copy(access = RegFieldAccessType.RWSPECIAL)})
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desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)})
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// This RegField wraps an explicit register
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// This RegField wraps an explicit register
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// (e.g. Black-Boxed Register) to create a R/W register.
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// (e.g. Black-Boxed Register) to create a R/W register.
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@ -151,7 +170,7 @@ object RegField
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bb.en := valid
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bb.en := valid
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bb.d := data
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bb.d := data
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Bool(true)
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Bool(true)
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}), desc.map{_.copy(access = RegFieldAccessType.RW)})
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}), desc)
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// Create byte-sized read-write RegFields out of a large UInt register.
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// Create byte-sized read-write RegFields out of a large UInt register.
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// It is updated when any of the bytes are written. Because the RegFields
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// It is updated when any of the bytes are written. Because the RegFields
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@ -89,15 +89,18 @@ case class TLRegisterNode(
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var currentBitOffset = 0
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var currentBitOffset = 0
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seq.zipWithIndex.map { case (f, i) => {
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seq.zipWithIndex.map { case (f, i) => {
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val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${offset.toHexString}_${currentBitOffset}") -> (
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val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${offset.toHexString}_${currentBitOffset}") -> (
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("byteOffset" -> s"0x${offset.toHexString}") ~
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("byteOffset" -> s"0x${offset.toHexString}") ~
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("bitOffset" -> currentBitOffset) ~
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("bitOffset" -> currentBitOffset) ~
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("bitWidth" -> f.width) ~
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("bitWidth" -> f.width) ~
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("name" -> f.desc.map(_.name)) ~
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("name" -> f.desc.map(_.name)) ~
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("description" -> f.desc.map{d => if (d.desc == "") None else Some(d.desc)}) ~
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("description" -> f.desc.map{d => if (d.desc == "") None else Some(d.desc)}) ~
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("resetValue" -> f.desc.map{_.reset}) ~
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("resetValue" -> f.desc.map{_.reset}) ~
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("group" -> f.desc.map{_.group}) ~
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("group" -> f.desc.map{_.group}) ~
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("groupDesc" -> f.desc.map{_.groupDesc}) ~
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("groupDesc" -> f.desc.map{_.groupDesc}) ~
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("accessType" -> f.desc.map {d => d.access.toString}) ~
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("accessType" -> f.desc.map {d => d.access.toString}) ~
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("writeType" -> f.desc.map {d => d.wrType.map(_.toString)}) ~
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("readAction" -> f.desc.map {d => d.rdAction.map(_.toString)}) ~
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("volatile" -> f.desc.map {d => if (d.volatile) Some(true) else None}) ~
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("enumerations" -> f.desc.map {d =>
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("enumerations" -> f.desc.map {d =>
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Option(d.enumerations.map { case (key, (name, desc)) =>
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Option(d.enumerations.map { case (key, (name, desc)) =>
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(("value" -> key) ~
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(("value" -> key) ~
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