riscv/rocket-chip
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improve PriorityEncoderOH and add Counter util

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This commit is contained in:
Andrew Waterman 2012-07-30 16:06:30 -07:00
parent 2af84f994a
commit 2ec76390e3
1 changed files with 18 additions and 6 deletions
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24
rocket/src/main/scala/util.scala
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@ -78,14 +78,26 @@ object PriorityEncoder
object PriorityEncoderOH object PriorityEncoderOH
{ {
def apply(in: Bits): UFix = doApply(in, 0) def apply(in: Bits): Bits = Vec(apply((0 until in.getWidth).map(in(_)))){Bits()}.toBits
def doApply(in: Bits, n: Int = 0): UFix = { def apply(in: Seq[Bits]): Seq[Bool] = {
val out = Vec(in.getWidth) { Bool() }
var none_hot = Bool(true) var none_hot = Bool(true)
for (i <- 0 until in.getWidth) { val out = collection.mutable.ArrayBuffer[Bool]()
out(i) := none_hot && in(i) for (i <- 0 until in.size) {
out += none_hot && in(i)
none_hot = none_hot && !in(i) none_hot = none_hot && !in(i)
} }
out.toBits out
}
}
object Counter
{
def apply(cond: Bool, n: Int) = {
val c = Reg(resetVal = UFix(0, log2Up(n)))
val wrap = c === UFix(n-1)
when (cond) {
c := Mux(Bool(!isPow2(n)) && wrap, UFix(0), c + UFix(1))
}
(c, wrap && cond)
} }
} }