riscv/rocket-chip
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Cache utility traits. Completely compiles, asm tests hang.

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Henry Cook committed 2014-08-19 11:38:20 -07:00
1 parent ca5f38ff26
commit 2de268b3b1
8 files changed
+281 -267
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rocket/src/main/scala/csr.scala
+1 -1
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@@ -160,7 +160,7 @@ class CSRFile extends Module
when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
val read_impl = Bits(2)
val read_ptbr = reg_ptbr(params(PAddrBits)-1, params(PgIdxBits)) << params(PgIdxBits)
val read_ptbr = reg_ptbr(params(PAddrBits)-1, params(PgIdxBits)) << UInt(params(PgIdxBits))
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
CSRs.fflags -> (if (!params(BuildFPU).isEmpty) reg_fflags else UInt(0)),