riscv/rocket-chip
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Cache utility traits. Completely compiles, asm tests hang.

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This commit is contained in:
Henry Cook
2014-08-11 18:36:23 -07:00
parent ca5f38ff26
commit 2de268b3b1
8 changed files with 281 additions and 267 deletions
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3
rocket/src/main/scala/core.scala
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@ -24,7 +24,8 @@ class Core extends Module
val dpath = Module(new Datapath)
if (!params(BuildFPU).isEmpty) {
val fpu = Module(params(BuildFPU).get(),params(FPUParams))
val p = Some(params.alter(params(FPUParams)))
val fpu = Module(params(BuildFPU).get())(p)
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
}