Cache utility traits. Completely compiles, asm tests hang.
This commit is contained in:
Henry Cook
@ -5,13 +5,18 @@ import Util._
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import Node._
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import uncore._
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case object Entries extends Field[Int]
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case object BTBEntries extends Field[Int]
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case object NRAS extends Field[Int]
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case object MatchBits extends Field[Int]
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case object Pages0 extends Field[Int]
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case object Pages extends Field[Int]
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case object OpaqueBits extends Field[Int]
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case object NBHT extends Field[Int]
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abstract trait BTBParameters extends UsesParameters {
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val vaddrBits = params(VAddrBits)
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val matchBits = params(PgIdxBits)
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val entries = params(BTBEntries)
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val nRAS = params(NRAS)
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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class RAS(nras: Int) {
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def push(addr: UInt): Unit = {
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@ -33,8 +38,8 @@ class RAS(nras: Int) {
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private val stack = Vec.fill(nras){Reg(UInt())}
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}
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class BHTResp extends Bundle {
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val index = UInt(width = log2Up(params(NBHT)).max(1))
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class BHTResp extends Bundle with BTBParameters {
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val index = UInt(width = log2Up(nBHT).max(1))
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val value = UInt(width = 2)
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}
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@ -55,11 +60,11 @@ class BHT(nbht: Int) {
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val history = Reg(UInt(width = nbhtbits))
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}
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class BTBUpdate extends Bundle {
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class BTBUpdate extends Bundle with BTBParameters {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = params(VAddrBits))
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val target = UInt(width = params(VAddrBits))
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val returnAddr = UInt(width = params(VAddrBits))
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val returnAddr = UInt(width = vaddrBits)
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val taken = Bool()
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val isJump = Bool()
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val isCall = Bool()
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@ -67,42 +72,42 @@ class BTBUpdate extends Bundle {
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val incorrectTarget = Bool()
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}
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class BTBResp extends Bundle {
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class BTBResp extends Bundle with BTBParameters {
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val taken = Bool()
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val target = UInt(width = params(VAddrBits))
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val entry = UInt(width = params(OpaqueBits))
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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val bht = new BHTResp
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}
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// fully-associative branch target buffer
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class BTB extends Module {
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class BTB extends Module with BTBParameters {
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val io = new Bundle {
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val req = UInt(INPUT, params(VAddrBits))
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val req = UInt(INPUT, vaddrBits)
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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}
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val idxValid = Reg(init=UInt(0, params(Entries)))
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val idxs = Mem(UInt(width=params(MatchBits)), params(Entries))
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val idxPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
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val tgts = Mem(UInt(width=params(MatchBits)), params(Entries))
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val tgtPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
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val pages = Mem(UInt(width=params(VAddrBits)-params(MatchBits)), params(Pages))
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val pageValid = Reg(init=UInt(0, params(Pages)))
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val idxPagesOH = idxPages.map(UIntToOH(_)(params(Pages)-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(params(Pages)-1,0))
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(UInt(width=matchBits), entries)
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val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
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val tgts = Mem(UInt(width=matchBits), entries)
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val tgtPages = Mem(UInt(width=log2Up(nPages)), entries)
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val pages = Mem(UInt(width=vaddrBits-matchBits), nPages)
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val pageValid = Reg(init=UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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val useRAS = Reg(UInt(width = params(Entries)))
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val isJump = Reg(UInt(width = params(Entries)))
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val useRAS = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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private def page(addr: UInt) = addr >> params(MatchBits)
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid
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}
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(params(MatchBits)-1,0)
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val idx = addr(matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid & idxMatch & idxPageMatch
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@ -123,7 +128,7 @@ class BTB extends Module {
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}
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val updateHit = update.bits.prediction.valid
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val updateValid = update.bits.incorrectTarget || updateHit && Bool(params(NBHT) > 0)
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val updateValid = update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && update.bits.incorrectTarget
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val useUpdatePageHit = updatePageHit.orR
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@ -136,20 +141,20 @@ class BTB extends Module {
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val samePage = page(update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(params(Pages)-2,0) << 1 | idxPageUpdateOH(params(Pages)-1))
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, params(Pages))._1)
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idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, nPages)._1)
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when (update.valid && !(updateValid && !updateTarget)) {
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val nextRepl = Counter(!updateHit && updateValid, params(Entries))._1
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val nextRepl = Counter(!updateHit && updateValid, entries)._1
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val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(params(Entries))(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
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@ -162,11 +167,11 @@ class BTB extends Module {
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isJump(waddr) := update.bits.isJump
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}
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require(params(Pages) % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(params(Pages)/2, UInt(1,2))).orR
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require(nPages % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(nPages/2, UInt(1,2))).orR
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
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for (i <- i until params(Pages) by mod)
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for (i <- i until nPages by mod)
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when (en && pageReplEn(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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@ -187,16 +192,16 @@ class BTB extends Module {
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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if (params(NBHT) > 0) {
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val bht = new BHT(params(NBHT))
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val res = bht.get(io.req)
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when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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}
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if (params(NRAS) > 0) {
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val ras = new RAS(params(NRAS))
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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val doPeek = Mux1H(hits, useRAS)
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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