Merge branch 'master' into jchang_test

src/main/scala/rocket/Frontend.scala

@@ -4,10 +4,11 @@
 package rocket
 
 import Chisel._
-import uncore.tilelink._
+import config._
+import diplomacy._
+import uncore.tilelink2._
 import util._
 import Chisel.ImplicitConversions._
-import config._
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)
@@ -34,15 +35,28 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val npc = UInt(INPUT, width = vaddrBitsExtended)
 }
 
-class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
+class Frontend(implicit p: Parameters) extends LazyModule {
-  val io = new Bundle {
+  lazy val module = new FrontendModule(this)
+  val icache = LazyModule(new ICache(latency = 2))
+  val node = TLOutputNode()
+
+  node := icache.node
+}
+
+class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
   val cpu = new FrontendIO().flip
   val ptw = new TLBPTWIO()
-    val mem = new ClientUncachedTileLinkIO
+  val mem = outer.node.bundleOut
   val resetVector = UInt(INPUT, vaddrBitsExtended)
-  }
+}
+
+class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
+    with HasCoreParameters
+    with HasL1CacheParameters {
+  val io = new FrontendBundle(outer)
+  implicit val edge = outer.node.edgesOut(0)
+  val icache = outer.icache.module
 
-  val icache = Module(new ICache(latency = 2))
   val tlb = Module(new TLB)
 
   val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))
@@ -115,7 +129,6 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
   tlb.io.req.bits.instruction := Bool(true)
   tlb.io.req.bits.store := Bool(false)
 
-  io.mem <> icache.io.mem
   icache.io.req.valid := !stall && !s0_same_block
   icache.io.req.bits.addr := io.cpu.npc
   icache.io.invalidate := io.cpu.flush_icache

src/main/scala/rocket/HellaCache.scala

@@ -20,22 +20,11 @@ case class DCacheConfig(
 
 case object DCacheKey extends Field[DCacheConfig]
 
-trait HasL1HellaCacheParameters extends HasCacheParameters with HasCoreParameters {
+trait HasL1HellaCacheParameters extends HasL1CacheParameters {
-  val outerDataBeats = p(TLKey(p(TLId))).dataBeats
-  val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
-
-  val refillCyclesPerBeat = outerDataBits/rowBits
-  require(refillCyclesPerBeat == 1)
-
-  val refillCycles = refillCyclesPerBeat*outerDataBeats
-
-  val cacheBlockBytes = p(CacheBlockBytes)
-  val lgCacheBlockBytes = log2Up(cacheBlockBytes)
-
   val wordBits = xLen // really, xLen max 
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
-  val beatBytes = cacheBlockBytes / outerDataBeats
+  val beatBytes = cacheBlockBytes / cacheDataBeats
   val beatWords = beatBytes / wordBytes
   val beatOffBits = log2Up(beatBytes)
   val idxMSB = untagBits-1
@@ -51,8 +40,8 @@ trait HasL1HellaCacheParameters extends HasCacheParameters with HasCoreParameter
 
   require(isPow2(nSets))
   require(rowBits >= coreDataBits)
-  require(rowBits <= outerDataBits)
+  require(rowBits == cacheDataBits) // TODO should rowBits even be seperably specifiable?
-  require(xLen <= outerDataBits) // would need offset addr for puts if data width < xlen
+  require(xLen <= cacheDataBits) // would need offset addr for puts if data width < xlen
   require(!usingVM || untagBits <= pgIdxBits)
 }
 
@@ -136,7 +125,8 @@ abstract class HellaCache(val cfg: DCacheConfig)(implicit p: Parameters) extends
   val module: HellaCacheModule
 }
 
-class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle {
+class HellaCacheBundle(outer: HellaCache) extends Bundle {
+  implicit val p = outer.p
   val cpu = (new HellaCacheIO).flip
   val ptw = new TLBPTWIO()
   val mem = outer.node.bundleOut
@@ -145,18 +135,9 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle
 class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
     with HasL1HellaCacheParameters {
   implicit val cfg = outer.cfg
+  implicit val edge = outer.node.edgesOut(0)
   val io = new HellaCacheBundle(outer)
   val tl_out = io.mem(0)
-
-  /* TODO
-  edge.manager.managers.foreach { m =>
-    if (m.supportsGet) {
-      require (m.supportsGet.contains(TransferSizes(1, tlDataBytes)))
-    ....etc
-    }
-  }
-  */
-
 }
 
 object HellaCache {

src/main/scala/rocket/ICache.scala

@@ -4,18 +4,20 @@
 package rocket
 
 import Chisel._
+import config._
+import diplomacy._
 import uncore.agents._
-import uncore.tilelink._
+import uncore.tilelink2._
 import uncore.util._
 import util._
 import Chisel.ImplicitConversions._
-import config._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
-  val outerDataBeats = p(TLKey(p(TLId))).dataBeats
+  val cacheBlockBytes = p(CacheBlockBytes)
-  val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
+  val lgCacheBlockBytes = log2Up(cacheBlockBytes)
-  val refillCyclesPerBeat = outerDataBits/rowBits
+  val cacheDataBits = p(TLCacheEdge).bundle.dataBits
-  val refillCycles = refillCyclesPerBeat*outerDataBeats
+  val cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
+  val refillCycles = cacheDataBeats
 }
 
 class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
@@ -27,8 +29,12 @@ class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1Cache
   val datablock = Bits(width = rowBits)
 }
 
-class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
+class ICache(val latency: Int)(implicit p: Parameters) extends LazyModule {
-  val io = new Bundle {
+  lazy val module = new ICacheModule(this)
+  val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
+}
+
+class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
   val req = Valid(new ICacheReq).flip
   val s1_ppn = UInt(INPUT, ppnBits) // delayed one cycle w.r.t. req
   val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
@@ -36,8 +42,16 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
 
   val resp = Decoupled(new ICacheResp)
   val invalidate = Bool(INPUT)
-    val mem = new ClientUncachedTileLinkIO
+  val mem = outer.node.bundleOut
-  }
+}
+
+class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
+    with HasCoreParameters
+    with HasL1CacheParameters {
+  val io = new ICacheBundle(outer)
+  val edge = outer.node.edgesOut(0)
+  val tl_out = io.mem(0)
+
   require(isPow2(nSets) && isPow2(nWays))
   require(isPow2(coreInstBytes))
   require(!usingVM || pgIdxBits >= untagBits)
@@ -74,12 +88,8 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
     refill_addr := s1_paddr
   }
   val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
-
+  val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d)
-  require(refillCyclesPerBeat == 1)
+  tl_out.d.ready := state === s_refill
-  val narrow_grant = io.mem.grant 
-  val (refill_cnt, refill_wrap) = Counter(narrow_grant.fire(), refillCycles)
-  val refill_done = state === s_refill && refill_wrap
-  narrow_grant.ready := Bool(true)
 
   val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
   val entagbits = code.width(tagBits)
@@ -118,9 +128,9 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
 
   for (i <- 0 until nWays) {
     val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits)))
-    val wen = narrow_grant.valid && repl_way === UInt(i)
+    val wen = tl_out.d.valid && repl_way === UInt(i)
     when (wen) {
-      val e_d = code.encode(narrow_grant.bits.data)
+      val e_d = code.encode(tl_out.d.bits.data)
       data_array.write((s1_idx << log2Ceil(refillCycles)) | refill_cnt, e_d)
     }
     val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
@@ -128,7 +138,7 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
   }
 
   // output signals
-  latency match {
+  outer.latency match {
     case 1 =>
       io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
       io.resp.valid := s1_hit
@@ -139,8 +149,13 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
       io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
       io.resp.valid := s2_hit
   }
-  io.mem.acquire.valid := state === s_request && !io.s2_kill
+  tl_out.a.valid := state === s_request && !io.s2_kill
-  io.mem.acquire.bits := GetBlock(addr_block = refill_addr >> blockOffBits)
+  tl_out.a.bits := edge.Get(
+                    fromSource = UInt(0),
+                    toAddress = (refill_addr >> blockOffBits) << blockOffBits,
+                    lgSize = lgCacheBlockBytes)._2
+  tl_out.c.valid := Bool(false)
+  tl_out.e.valid := Bool(false)
 
   // control state machine
   switch (state) {
@@ -149,11 +164,11 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
       invalidated := Bool(false)
     }
     is (s_request) {
-      when (io.mem.acquire.ready) { state := s_refill_wait }
+      when (tl_out.a.ready) { state := s_refill_wait }
       when (io.s2_kill) { state := s_ready }
     }
     is (s_refill_wait) {
-      when (io.mem.grant.valid) { state := s_refill }
+      when (tl_out.d.valid) { state := s_refill }
     }
     is (s_refill) {
       when (refill_done) { state := s_ready }

src/main/scala/rocket/NBDcache.scala

@@ -62,7 +62,7 @@ class WritebackReq(params: TLBundleParameters)(implicit p: Parameters) extends L
   override def cloneType = new WritebackReq(params)(p).asInstanceOf[this.type]
 }
 
-class IOMSHR(id: Int, edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
+class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new HellaCacheReq).flip
     val resp = Decoupled(new HellaCacheResp)
@@ -145,7 +145,7 @@ class IOMSHR(id: Int, edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCa
   }
 }
 
-class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters) extends L1HellaCacheModule()(p) {
+class MSHR(id: Int)(implicit edge: TLEdgeOut, cfg: DCacheConfig, p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req_pri_val    = Bool(INPUT)
     val req_pri_rdy    = Bool(OUTPUT)
@@ -310,7 +310,7 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
   }
 }
 
-class MSHRFile(edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters) extends L1HellaCacheModule()(p) {
+class MSHRFile(implicit edge: TLEdgeOut, cfg: DCacheConfig, p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new MSHRReq).flip
     val resp = Decoupled(new HellaCacheResp)
@@ -361,7 +361,7 @@ class MSHRFile(edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters) exten
   io.probe_rdy := true
 
   val mshrs = (0 until cfg.nMSHRs) map { i =>
-    val mshr = Module(new MSHR(i,edge)(cfg,p))
+    val mshr = Module(new MSHR(i))
 
     idxMatch(i) := mshr.io.idx_match
     tagList(i) := mshr.io.tag
@@ -408,7 +408,7 @@ class MSHRFile(edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters) exten
 
   val mmios = (0 until nIOMSHRs) map { i =>
     val id = cfg.nMSHRs + i
-    val mshr = Module(new IOMSHR(id, edge))
+    val mshr = Module(new IOMSHR(id))
 
     mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
     mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
@@ -449,7 +449,7 @@ class MSHRFile(edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters) exten
   }
 }
 
-class WritebackUnit(edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
+class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new WritebackReq(edge.bundle)).flip
     val meta_read = Decoupled(new L1MetaReadReq)
@@ -525,7 +525,7 @@ class WritebackUnit(edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCach
   io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)
 }
 
-class ProbeUnit(edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
+class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new TLBundleB(edge.bundle)).flip
     val rep = Decoupled(new TLBundleC(edge.bundle))
@@ -680,9 +680,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   require(isPow2(nWays)) // TODO: relax this
   require(p(DataScratchpadSize) == 0)
 
-  val wb = Module(new WritebackUnit(edge))
+  val wb = Module(new WritebackUnit)
-  val prober = Module(new ProbeUnit(edge))
+  val prober = Module(new ProbeUnit)
-  val mshrs = Module(new MSHRFile(edge))
+  val mshrs = Module(new MSHRFile)
 
   io.cpu.req.ready := Bool(true)
   val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))

src/main/scala/rocket/TLB.scala

@@ -15,9 +15,8 @@ import uncore.tilelink2._
 case object PgLevels extends Field[Int]
 case object ASIdBits extends Field[Int]
 
-trait HasTLBParameters extends HasCoreParameters {
+trait HasTLBParameters extends HasL1CacheParameters {
   val entries = p(p(CacheName)).nTLBEntries
-  val cacheBlockBytes = p(CacheBlockBytes)
   val camAddrBits = log2Ceil(entries)
   val camTagBits = asIdBits + vpnBits
 }
@@ -39,7 +38,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
   val cacheable = Bool(OUTPUT)
 }
 
-class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
+class TLB(implicit edge: TLEdgeOut, val p: Parameters) extends Module with HasTLBParameters {
   val io = new Bundle {
     val req = Decoupled(new TLBReq).flip
     val resp = new TLBResp
@@ -179,7 +178,7 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
   }
 }
 
-class DecoupledTLB(implicit p: Parameters) extends Module {
+class DecoupledTLB(implicit edge: TLEdgeOut, p: Parameters) extends Module {
   val io = new Bundle {
     val req = Decoupled(new TLBReq).flip
     val resp = Decoupled(new TLBResp)

src/main/scala/rocket/Tile.scala

@@ -36,7 +36,6 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
     case TLId => "L1toL2"
   })
 
-  //TODO val intNode = IntInputNode()
   val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
   val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
   def findScratch() = scratch.map { s =>
@@ -47,12 +46,16 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   }
 
   val dcache = HellaCache(p(DCacheKey), findScratch)(dcacheParams)
+  val frontend = LazyModule(new Frontend()(icacheParams))
   val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
+  val tileXbar = LazyModule(new TLXbar)
+  tileXbar.node := TLHintHandler()(ucLegacy.node)
+  tileXbar.node := frontend.node
 
   val cachedOut = TLOutputNode()
   val uncachedOut = TLOutputNode()
   cachedOut := dcache.node
-  uncachedOut := TLHintHandler()(ucLegacy.node)
+  uncachedOut := tileXbar.node
   val masterNodes = List(cachedOut, uncachedOut)
 
   (slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
@@ -73,15 +76,14 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
     val nFPUPorts = buildRocc.filter(_.useFPU).size
 
     val core = Module(new Rocket()(dcacheParams))
-    val icache = Module(new Frontend()(icacheParams))
 
-    val ptwPorts = ListBuffer(icache.io.ptw, dcache.module.io.ptw)
+    val ptwPorts = ListBuffer(frontend.module.io.ptw, dcache.module.io.ptw)
     val dcPorts = ListBuffer(core.io.dmem)
-    val uncachedArbPorts = ListBuffer(icache.io.mem)
+    val uncachedArbPorts = ListBuffer[ClientUncachedTileLinkIO]()
     core.io.interrupts := io.interrupts
     core.io.hartid := io.hartid
-    icache.io.cpu <> core.io.imem
+    frontend.module.io.cpu <> core.io.imem
-    icache.io.resetVector := io.resetVector
+    frontend.module.io.resetVector := io.resetVector
 
     val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams)))
     fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
@@ -129,11 +131,14 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
 
       ptwPorts ++= roccs.flatMap(_.io.ptw)
       uncachedArbPorts ++= roccs.flatMap(_.io.utl) // TODO no difference between io.autl and io.utl for now
-    }
 
       val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)(icacheParams))
       uncachedArb.io.in <> uncachedArbPorts
       ucLegacy.module.io.legacy <> uncachedArb.io.out
+    } else {
+      ucLegacy.module.io.legacy.acquire.valid := Bool(false)
+      ucLegacy.module.io.legacy.grant.ready := Bool(false)
+    }
 
     if (p(UseVM)) {
       val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))

src/main/scala/rocket/rocket.scala

@@ -5,7 +5,7 @@ package rocket
 
 import Chisel._
 import uncore.devices._
-import uncore.util.CacheName
+import uncore.util.{CacheName, CacheBlockBytes}
 import uncore.constants._
 import uncore.tilelink2._
 import util._
@@ -40,7 +40,6 @@ trait HasCoreParameters {
   val xLen = p(XLen)
   val fLen = xLen // TODO relax this
 
-  val edge = p(TLCacheEdge)
   val usingVM = p(UseVM)
   val usingUser = p(UseUser) || usingVM
   val usingDebug = p(UseDebug)
@@ -70,7 +69,7 @@ trait HasCoreParameters {
   def pgIdxBits = 12
   def pgLevelBits = 10 - log2Ceil(xLen / 32)
   def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
-  val paddrBits = edge.bundle.addressBits
+  val paddrBits = p(TLCacheEdge).bundle.addressBits
   def ppnBits = paddrBits - pgIdxBits
   def vpnBits = vaddrBits - pgIdxBits
   val pgLevels = p(PgLevels)