riscv/rocket-chip
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set pending_writes for puts

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This commit is contained in:
Yunsup Lee 2015-03-17 18:35:04 -07:00
parent 504eedbf89
commit 2d7375760d
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@ -814,7 +814,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
pending_reads := Mux(io.iacq().isSubBlockType(), pending_reads := Mux(io.iacq().isSubBlockType(),
UIntToOH(io.iacq().addr_beat), UIntToOH(io.iacq().addr_beat),
SInt(-1, width = innerDataBeats)).toUInt SInt(-1, width = innerDataBeats)).toUInt
pending_writes := UInt(0) pending_writes := addPendingBit(io.inner.acquire)
pending_resps := UInt(0) pending_resps := UInt(0)
ifin_cnt := UInt(0) ifin_cnt := UInt(0)
ignt_q.io.enq.valid := Bool(true) ignt_q.io.enq.valid := Bool(true)