From 2d6b3b23313b9a74e35fd0c48b54615052b13395 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 15 Jul 2015 18:06:27 -0700 Subject: [PATCH] Don't use clone --- uncore/src/main/scala/cache.scala | 14 +++++++------- uncore/src/main/scala/memserdes.scala | 6 +++--- uncore/src/main/scala/network.scala | 12 ++++++------ uncore/src/main/scala/tilelink.scala | 10 +++++----- uncore/src/main/scala/uncore.scala | 2 +- uncore/src/main/scala/util.scala | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 721ff5a1..012156c5 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -135,16 +135,16 @@ class MetaReadReq extends CacheBundle { class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq { val way_en = Bits(width = nWays) - val data = gen.clone - override def clone = new MetaWriteReq(gen).asInstanceOf[this.type] + val data = gen.cloneType + override def cloneType = new MetaWriteReq(gen).asInstanceOf[this.type] } class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule { val rstVal = makeRstVal() val io = new Bundle { val read = Decoupled(new MetaReadReq).flip - val write = Decoupled(new MetaWriteReq(rstVal.clone)).flip - val resp = Vec.fill(nWays){rstVal.clone.asOutput} + val write = Decoupled(new MetaWriteReq(rstVal)).flip + val resp = Vec.fill(nWays){rstVal.cloneType.asOutput} } val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1))) val rst = rst_cnt < UInt(nSets) @@ -186,7 +186,7 @@ abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters { def doInternalOutputArbitration[T <: Data : ClassTag]( out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) { - val arb = Module(new RRArbiter(out.bits.clone, ins.size)) + val arb = Module(new RRArbiter(out.bits, ins.size)) out <> arb.io.out arb.io.in <> ins } @@ -237,7 +237,7 @@ class L2MetaReadReq extends MetaReadReq with HasL2Id { class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata) with HasL2Id { - override def clone = new L2MetaWriteReq().asInstanceOf[this.type] + override def cloneType = new L2MetaWriteReq().asInstanceOf[this.type] } class L2MetaResp extends L2HellaCacheBundle @@ -591,7 +591,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker { val xact_tag_match = Reg{ Bool() } val xact_way_en = Reg{ Bits(width = nWays) } val xact_old_meta = Reg{ new L2Metadata } - val pending_coh = Reg{ xact_old_meta.coh.clone } + val pending_coh = Reg{ xact_old_meta.coh } // Secondary miss queue val ignt_q = Module(new Queue(new SecondaryMissInfo, nSecondaryMisses))(innerTLParams) diff --git a/uncore/src/main/scala/memserdes.scala b/uncore/src/main/scala/memserdes.scala index 029541ff..b58553bb 100644 --- a/uncore/src/main/scala/memserdes.scala +++ b/uncore/src/main/scala/memserdes.scala @@ -415,7 +415,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data val mif_done_in = Reg(init=Bool(false)) val mif_buf_in = Reg(Vec(new MemData, mifDataBeats)) - val tl_buf_in = Vec.fill(tlDataBeats){ io.tl.acquire.bits.data.clone } + val tl_buf_in = Vec.fill(tlDataBeats){ io.tl.acquire.bits.data } tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits) val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits) val mif_prog_in = mif_cnt_in*UInt(mifDataBits) @@ -506,7 +506,7 @@ class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module object HellaQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = { - val q = Module((new HellaQueue(entries)) { enq.bits.clone }) + val q = Module((new HellaQueue(entries)) { enq.bits }) q.io.enq.valid := enq.valid // not using <> so that override is allowed q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready @@ -522,7 +522,7 @@ class MemIOArbiter(val arbN: Int) extends MIFModule { if(arbN > 1) { val cmd_arb = Module(new RRArbiter(new MemReqCmd, arbN)) - val choice_q = Module(new Queue(cmd_arb.io.chosen.clone, 4)) + val choice_q = Module(new Queue(cmd_arb.io.chosen, 4)) val (data_cnt, data_done) = Counter(io.outer.req_data.fire(), mifDataBeats) io.inner.map(_.req_cmd).zipWithIndex.zip(cmd_arb.io.in).map{ case ((req, id), arb) => { diff --git a/uncore/src/main/scala/network.scala b/uncore/src/main/scala/network.scala index 4b00091d..9170982f 100644 --- a/uncore/src/main/scala/network.scala +++ b/uncore/src/main/scala/network.scala @@ -13,8 +13,8 @@ class PhysicalHeader(n: Int) extends Bundle { class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle { val header = new PhysicalHeader(n) - val payload = dType.clone - override def clone = new PhysicalNetworkIO(n,dType).asInstanceOf[this.type] + val payload = dType + override def cloneType = new PhysicalNetworkIO(n,dType).asInstanceOf[this.type] } class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle { @@ -52,8 +52,8 @@ class LogicalHeader extends Bundle { class LogicalNetworkIO[T <: Data](dType: T) extends Bundle { val header = new LogicalHeader - val payload = dType.clone - override def clone = { new LogicalNetworkIO(dType).asInstanceOf[this.type] } + val payload = dType.cloneType + override def cloneType = new LogicalNetworkIO(dType).asInstanceOf[this.type] } object DecoupledLogicalNetworkIOWrapper { @@ -61,7 +61,7 @@ object DecoupledLogicalNetworkIOWrapper { in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0)): DecoupledIO[LogicalNetworkIO[T]] = { - val out = Decoupled(new LogicalNetworkIO(in.bits.clone)).asDirectionless + val out = Decoupled(new LogicalNetworkIO(in.bits)).asDirectionless out.valid := in.valid out.bits.payload := in.bits out.bits.header.dst := dst @@ -73,7 +73,7 @@ object DecoupledLogicalNetworkIOWrapper { object DecoupledLogicalNetworkIOUnwrapper { def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[T] = { - val out = Decoupled(in.bits.payload.clone).asDirectionless + val out = Decoupled(in.bits.payload).asDirectionless out.valid := in.valid out.bits := in.bits.payload in.ready := out.ready diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 31f0b136..c8f6951c 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -904,7 +904,7 @@ object ClientTileLinkHeaderCreator { in: DecoupledIO[T], clientId: Int, addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = { - val out = new DecoupledIO(new LogicalNetworkIO(in.bits.clone)).asDirectionless + val out = new DecoupledIO(new LogicalNetworkIO(in.bits)).asDirectionless out.bits.payload := in.bits out.bits.header.src := UInt(clientId) out.bits.header.dst := addrConvert(in.bits.addr_block) @@ -943,7 +943,7 @@ object ManagerTileLinkHeaderCreator { in: DecoupledIO[T], managerId: Int, idConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = { - val out = new DecoupledIO(new LogicalNetworkIO(in.bits.clone)).asDirectionless + val out = new DecoupledIO(new LogicalNetworkIO(in.bits)).asDirectionless out.bits.payload := in.bits out.bits.header.src := UInt(managerId) out.bits.header.dst := idConvert(in.bits.client_id) @@ -1001,7 +1001,7 @@ trait TileLinkArbiterLike extends TileLinkParameters { clts: Seq[DecoupledIO[LogicalNetworkIO[M]]], mngr: DecoupledIO[LogicalNetworkIO[M]]) { def hasData(m: LogicalNetworkIO[M]) = m.payload.hasMultibeatData() - val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, tlDataBeats, Some(hasData _))) + val arb = Module(new LockingRRArbiter(mngr.bits, arbN, tlDataBeats, Some(hasData _))) clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => { arb.valid := req.valid arb.bits := req.bits @@ -1015,7 +1015,7 @@ trait TileLinkArbiterLike extends TileLinkParameters { clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) { def hasData(m: M) = m.hasMultibeatData() - val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, tlDataBeats, Some(hasData _))) + val arb = Module(new LockingRRArbiter(mngr.bits, arbN, tlDataBeats, Some(hasData _))) clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => { arb.valid := req.valid arb.bits := req.bits @@ -1076,7 +1076,7 @@ trait TileLinkArbiterLike extends TileLinkParameters { } def hookupFinish[M <: LogicalNetworkIO[Finish]]( clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) { - val arb = Module(new RRArbiter(mngr.bits.clone, arbN)) + val arb = Module(new RRArbiter(mngr.bits, arbN)) arb.io.in <> clts arb.io.out <> mngr } diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala index a6ca291f..9b53832b 100644 --- a/uncore/src/main/scala/uncore.scala +++ b/uncore/src/main/scala/uncore.scala @@ -33,7 +33,7 @@ trait HasCoherenceAgentWiringHelpers { out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) { def lock(o: T) = o.hasMultibeatData() - val arb = Module(new LockingRRArbiter(out.bits.clone, ins.size, out.bits.tlDataBeats, lock _)) + val arb = Module(new LockingRRArbiter(out.bits, ins.size, out.bits.tlDataBeats, lock _)) out <> arb.io.out arb.io.in <> ins } diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala index 65c5d6cd..ff982e3f 100644 --- a/uncore/src/main/scala/util.scala +++ b/uncore/src/main/scala/util.scala @@ -44,8 +44,8 @@ object ZCounter { class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module { val io = new Bundle { - val in = Decoupled(gen.clone).flip - val out = Decoupled(gen.clone) + val in = Decoupled(gen).flip + val out = Decoupled(gen) val cnt = UInt(OUTPUT, log2Up(n)) val done = Bool(OUTPUT) } @@ -59,7 +59,7 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module } else { val cnt = Reg(init=UInt(0, width = log2Up(n))) val wrap = cnt === UInt(n-1) - val rbits = Reg(io.in.bits.clone) + val rbits = Reg{io.in.bits} val active = Reg(init=Bool(false)) val shifter = Vec.fill(n){Bits(width = narrowWidth)}