riscv/rocket-chip
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[tl2] give groundtest tile some output nodes

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This commit is contained in:
Henry Cook
2016-11-14 18:09:17 -08:00
parent ab3dafb8bc
commit 2d68f12115
1 changed files with 8 additions and 2 deletions
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10
src/main/scala/groundtest/Tile.scala
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@@ -105,10 +105,16 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()
cachedOut := dcache.node
uncachedOut := ucLegacy.node
val masterNodes = List(cachedOut, uncachedOut)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val cached = dcache.node.bundleOut
val uncached = ucLegacy.node.bundleOut
val cached = cachedOut.bundleOut
val uncached = uncachedOut.bundleOut
val success = Bool(OUTPUT)
}