riscv/rocket-chip
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Improve PTW simulation performance

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This commit is contained in:
Andrew Waterman 2016-07-02 14:34:18 -07:00
parent 5aa8ef1855
commit 2d325df60c
1 changed files with 7 additions and 8 deletions
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15
rocket/src/main/scala/ptw.scala
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@ -88,21 +88,20 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val (pte_cache_hit, pte_cache_data) = {
val size = log2Up(pgLevels * 2)
val plru = new PseudoLRU(size)
val valid = Reg(Vec(size, Bool()))
val validBits = valid.toBits
val tags = Mem(size, UInt(width = paddrBits))
val data = Mem(size, UInt(width = ppnBits))
val valid = Reg(init = UInt(0, size))
val tags = Reg(Vec(size, UInt(width = paddrBits)))
val data = Reg(Vec(size, UInt(width = ppnBits)))
val hits = Vec(tags.map(_ === pte_addr)).toBits & validBits
val hits = Vec(tags.map(_ === pte_addr)).toBits & valid
val hit = hits.orR
when (io.mem.resp.valid && pte.table() && !hit) {
val r = Mux(validBits.andR, plru.replace, PriorityEncoder(~validBits))
valid(r) := true
val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := pte_addr
data(r) := pte.ppn
}
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (reset || io.dpath.invalidate) { valid.foreach(_ := false) }
when (io.dpath.invalidate) { valid := 0 }
(hit, Mux1H(hits, data))
}