From 2d2096e50918eb2176845ebf60b71488682534b9 Mon Sep 17 00:00:00 2001
From: mwachs5 <megan@sifive.com>
Date: Wed, 15 Jun 2016 15:07:43 -0700
Subject: [PATCH] Add smaller ROM/RAM for 32-bit debug (#60)

---
 uncore/src/main/scala/debug.scala | 38 +++++++++++++++++++++++--------
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index 76f9e1d8..daa86b82 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -64,12 +64,10 @@ object DsbBusConsts {
   def sbAddrWidth = 12
   def sbIdWidth   = 10 
 
-  /* These are the default ROM contents, which support
-   * RV32 and RV64. RV128 are implemented as NOP.
-   * See the Debug Specification for the code.
-   */
-
-  // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h
+  //These are the default ROM contents, which support
+  //RV32 and RV64. RV128 are implemented as NOP.
+  // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
+  // The code assumes 4*0xF bytes of Debug RAM.
 
   def defaultRomContents : Array[Byte] = Array(
     0x6f, 0x00, 0x00, 0x06, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
@@ -88,6 +86,24 @@ object DsbBusConsts {
     0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
     0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
     0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0xdf, 0xfb).map(x => x.toByte)
+
+  // These ROM contents support only RV32 
+  // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
+  // The code assumes only 28 bytes of Debug RAM.
+
+  def xlen32OnlyRomContents : Array[Byte] = Array(
+    0x6f, 0x00, 0x00, 0x04, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
+    0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
+    0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
+    0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
+    0x63, 0x04, 0x04, 0x00, 0x6f, 0x00, 0x80, 0x03, 0x73, 0x24, 0x20, 0x7b,
+    0x73, 0x00, 0x20, 0x7b, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b,
+    0x13, 0x74, 0x04, 0x1c, 0x13, 0x04, 0x04, 0xf4, 0x63, 0x18, 0x04, 0x00,
+    0x0f, 0x10, 0x00, 0x00, 0x23, 0x2c, 0x90, 0x40, 0x67, 0x00, 0x00, 0x40,
+    0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10, 0x73, 0x60, 0x04, 0x7b,
+    0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02, 0xe3, 0x0c, 0x04, 0xfe,
+    0x6f, 0xf0, 0xdf, 0xfd).map(x => x.toByte)
+
 }
 
 
@@ -144,7 +160,7 @@ import DebugModuleAccessType._
   *  nComponents : The number of components to support debugging.
   *  nDebugBusAddrSize : Size of the Debug Bus Address
   *  nDebugRam Bytes: Size of the Debug RAM (depends on the XLEN of the machine).
-  *  debugRomContents: 
+  *  debugRomContents: Optional Sequence of bytes which form the Debug ROM contents. 
   *  hasBusMaster: Whether or not a bus master should be included
   *    The size of the accesses supported by the Bus Master. 
   *  nSerialPorts : Number of serial ports to instantiate
@@ -221,11 +237,15 @@ class DefaultDebugModuleConfig (val ncomponents : Int, val xlen:Int)
       // the ROM image would need to be
       // adjusted accordingly.
       nDebugRamBytes = xlen match{
-        case 32  => 64 
+        case 32  => 28 
         case 64  => 64
         case 128 => 64
       },
-      debugRomContents = Some(DsbBusConsts.defaultRomContents),
+      debugRomContents = xlen match {
+        case 32  => Some(DsbBusConsts.xlen32OnlyRomContents)
+        case 64  => Some(DsbBusConsts.defaultRomContents)
+        case 128 => Some(DsbBusConsts.defaultRomContents)
+      },
       hasBusMaster = false,
       hasAccess128 = false, 
       hasAccess64 = false,