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tilelink: ToAXI4 makes R channel errors sticky

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This commit is contained in:
Wesley W. Terpstra
2017-10-30 13:35:56 -07:00
parent d6f1612812
commit 2d12ddb4ed
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/tilelink/ToAXI4.scala
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@@ -176,7 +176,10 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_error = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val b_error = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
val r_d = edgeIn.AccessAck(r_source, r_size, UInt(0), r_error) val reg_error = RegInit(Bool(false))
when (out.r.fire()) { reg_error := !out.r.bits.last && (reg_error || r_error) }
val r_d = edgeIn.AccessAck(r_source, r_size, UInt(0), reg_error || r_error)
val b_d = edgeIn.AccessAck(b_source, b_size, b_error) val b_d = edgeIn.AccessAck(b_source, b_size, b_error)
in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits := Mux(r_wins, r_d, b_d)