riscv/rocket-chip
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simplify cpu-cache interface

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This commit is contained in:
Andrew Waterman 2012-02-26 18:26:29 -08:00
parent ad713a5d83
commit 2d04664a98
4 changed files with 12 additions and 37 deletions
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23
rocket/src/main/scala/cpu.scala
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@ -67,7 +67,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
dtlbarb.io.in(DTLB_CPU).bits.kill := ctrl.io.dtlb_kill
dtlbarb.io.in(DTLB_CPU).bits.cmd := ctrl.io.dmem.req_cmd
dtlbarb.io.in(DTLB_CPU).bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
dtlbarb.io.in(DTLB_CPU).bits.vpn := dpath.io.dmem.req_addr(VADDR_BITS,PGIDX_BITS)
dtlbarb.io.in(DTLB_CPU).bits.vpn := dpath.io.dtlb.vpn
ctrl.io.dtlb_rdy := dtlbarb.io.in(DTLB_CPU).ready
ctrl.io.xcpt_dtlb_ld := chosen_cpu && dtlb.io.cpu_resp.xcpt_ld
@ -83,7 +83,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
dtlb.io.cpu_req.bits.kill := ctrl.io.dtlb_kill
dtlb.io.cpu_req.bits.cmd := ctrl.io.dmem.req_cmd
dtlb.io.cpu_req.bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
dtlb.io.cpu_req.bits.vpn := dpath.io.dmem.req_addr(VADDR_BITS,PGIDX_BITS)
dtlb.io.cpu_req.bits.vpn := dpath.io.dtlb.vpn
ctrl.io.xcpt_dtlb_ld := dtlb.io.cpu_resp.xcpt_ld
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu_resp.xcpt_st
ctrl.io.dtlb_rdy := dtlb.io.cpu_req.ready
@ -129,23 +129,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
io.imem.itlb_miss := itlb.io.cpu.resp_miss;
// connect arbiter to ctrl+dpath+DTLB
arb.io.requestor(0).req_val := ctrl.io.dmem.req_val;
arb.io.requestor(0).req_cmd := ctrl.io.dmem.req_cmd;
arb.io.requestor(0).req_type := ctrl.io.dmem.req_type;
arb.io.requestor(0).req_kill := ctrl.io.dmem.req_kill;
arb.io.requestor(0).req_idx := dpath.io.dmem.req_addr(PGIDX_BITS-1,0);
arb.io.requestor(0).req_data := dpath.io.dmem.req_data;
arb.io.requestor(0).req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.resp_miss := arb.io.requestor(0).resp_miss;
ctrl.io.dmem.resp_replay:= arb.io.requestor(0).resp_replay;
ctrl.io.dmem.resp_nack := arb.io.requestor(0).resp_nack;
dpath.io.dmem.resp_val := arb.io.requestor(0).resp_val;
dpath.io.dmem.resp_miss := arb.io.requestor(0).resp_miss;
dpath.io.dmem.resp_replay := arb.io.requestor(0).resp_replay;
dpath.io.dmem.resp_type := io.dmem.resp_type;
dpath.io.dmem.resp_tag := arb.io.requestor(0).resp_tag;
dpath.io.dmem.resp_data := arb.io.requestor(0).resp_data;
dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;
arb.io.requestor(0) <> ctrl.io.dmem
arb.io.requestor(0) <> dpath.io.dmem
var fpu: rocketFPU = null
if (HAVE_FPU)

20
rocket/src/main/scala/dpath.scala
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@ -7,20 +7,6 @@ import Constants._
import Instructions._
import hwacha._
class ioDpathDmem extends Bundle()
{
val req_addr = UFix(VADDR_BITS+1, OUTPUT);
val req_tag = UFix(CPU_TAG_BITS, OUTPUT);
val req_data = Bits(64, OUTPUT);
val resp_val = Bool(INPUT);
val resp_miss = Bool(INPUT);
val resp_replay = Bool(INPUT);
val resp_type = Bits(3, INPUT);
val resp_tag = Bits(CPU_TAG_BITS, INPUT);
val resp_data = Bits(64, INPUT);
val resp_data_subword = Bits(64, INPUT);
}
class ioDpathImem extends Bundle()
{
val req_addr = UFix(VADDR_BITS+1, OUTPUT);
@ -32,7 +18,8 @@ class ioDpathAll extends Bundle()
val host = new ioHTIF();
val ctrl = new ioCtrlDpath().flip();
val debug = new ioDebug();
val dmem = new ioDpathDmem();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
val dtlb = new ioDTLB_CPU_req_bundle(List("vpn"))
val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "req_tag", "resp_val", "resp_data", "resp_type", "resp_tag"))
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
@ -283,9 +270,10 @@ class rocketDpath extends Component
// D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module
io.dmem.req_addr := ex_effective_address.toUFix;
io.dmem.req_idx := ex_effective_address
io.dmem.req_data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.dmem.req_tag := Cat(Mux(io.ctrl.ex_ext_mem_val, ex_reg_ext_mem_tag(CPU_TAG_BITS-2, 0), Cat(ex_reg_waddr, io.ctrl.ex_fp_val)), io.ctrl.ex_ext_mem_val).toUFix
io.dtlb.vpn := ex_effective_address >> UFix(PGIDX_BITS)
// processor control regfile read
pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;

2
rocket/src/main/scala/dtlb.scala
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@ -9,7 +9,7 @@ import hwacha._
// ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala
// should keep them in sync
class ioDTLB_CPU_req_bundle extends Bundle
class ioDTLB_CPU_req_bundle(view: List[String] = null) extends Bundle(view)
{
// lookup requests
val kill = Bool()

4
rocket/src/main/scala/ptw.scala
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@ -60,6 +60,8 @@ class rocketDmemArbiter(n: Int) extends Component
io.requestor(i).resp_val := io.dmem.resp_val && tag_hit
io.requestor(i).resp_replay := io.dmem.resp_replay && tag_hit
io.requestor(i).resp_data := io.dmem.resp_data
io.requestor(i).resp_data_subword := io.dmem.resp_data_subword
io.requestor(i).resp_type := io.dmem.resp_type
io.requestor(i).resp_tag := io.dmem.resp_tag >> UFix(log2up(n))
}
}
@ -68,7 +70,7 @@ class ioPTW extends Bundle
{
val itlb = new ioTLB_PTW().flip();
val dtlb = new ioTLB_PTW().flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_ppn", "req_idx", "resp_data", "resp_val", "resp_nack")).flip();
val dmem = new ioDmem().flip()
val ptbr = UFix(PADDR_BITS, INPUT);
}