simplify cpu-cache interface
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@ -60,6 +60,8 @@ class rocketDmemArbiter(n: Int) extends Component
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io.requestor(i).resp_val := io.dmem.resp_val && tag_hit
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io.requestor(i).resp_replay := io.dmem.resp_replay && tag_hit
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io.requestor(i).resp_data := io.dmem.resp_data
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io.requestor(i).resp_data_subword := io.dmem.resp_data_subword
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io.requestor(i).resp_type := io.dmem.resp_type
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io.requestor(i).resp_tag := io.dmem.resp_tag >> UFix(log2up(n))
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}
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}
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@ -68,7 +70,7 @@ class ioPTW extends Bundle
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{
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val itlb = new ioTLB_PTW().flip();
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val dtlb = new ioTLB_PTW().flip();
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val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_ppn", "req_idx", "resp_data", "resp_val", "resp_nack")).flip();
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val dmem = new ioDmem().flip()
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val ptbr = UFix(PADDR_BITS, INPUT);
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}
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