From 546205b174bb9e1ccc38eb0f8dc33b769cfc1a0a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 5 Aug 2015 15:28:31 -0700
Subject: [PATCH 01/35] Chisel3 compatibility: use >>Int instead of >>UInt

---
 rocket/src/main/scala/arbiter.scala  | 4 ++--
 rocket/src/main/scala/fpu.scala      | 2 +-
 rocket/src/main/scala/icache.scala   | 4 ++--
 rocket/src/main/scala/nbdcache.scala | 4 ++--
 rocket/src/main/scala/ptw.scala      | 2 +-
 rocket/src/main/scala/rocket.scala   | 2 +-
 6 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index b2a8482f..01d592a5 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -43,12 +43,12 @@ class HellaCacheArbiter(n: Int) extends Module
     io.requestor(i).xcpt := io.mem.xcpt
     io.requestor(i).ordered := io.mem.ordered
     resp.bits := io.mem.resp.bits
-    resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
+    resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
     resp.bits.nack := io.mem.resp.bits.nack && tag_hit
     resp.bits.replay := io.mem.resp.bits.replay && tag_hit
 
     io.requestor(i).replay_next.valid := io.mem.replay_next.valid &&
       io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(i)
-    io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
+    io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> log2Up(n)
   }
 }
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index aba5d61b..3b5810b8 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -215,7 +215,7 @@ class FPToInt extends Module
   dcmp.io.a := in.in1
   dcmp.io.b := in.in2
   val dcmp_out = (~in.rm & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
-  val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UInt(4)
+  val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << 4
 
   val d2i = hardfloat.recodedFloatNToAny(in.in1, in.rm, in.typ ^ 1, 52, 12, 64)
 
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 18e55b86..50294282 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -95,7 +95,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
 
   io.ptw <> tlb.io.ptw
   tlb.io.req.valid := !stall && !icmiss
-  tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits)
+  tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
   tlb.io.req.bits.asid := UInt(0)
   tlb.io.req.bits.passthrough := Bool(false)
   tlb.io.req.bits.instruction := Bool(true)
@@ -257,7 +257,7 @@ class ICache extends FrontendModule
   // output signals
   io.resp.valid := s2_hit
   io.mem.acquire.valid := (state === s_request)
-  io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
+  io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> blockOffBits)
 
   // control state machine
   switch (state) {
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index ac48b7b3..f58cc29e 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -332,7 +332,7 @@ class MSHRFile extends L1HellaCacheModule {
 
     idxMatch(i) := mshr.io.idx_match
     tagList(i) := mshr.io.tag
-    wbTagList(i) := mshr.io.wb_req.bits.addr_block >> UInt(idxBits)
+    wbTagList(i) := mshr.io.wb_req.bits.addr_block >> idxBits
 
     alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
     mshr.io.req_pri_val := alloc_arb.io.in(i).ready
@@ -437,7 +437,7 @@ class WritebackUnit extends L1HellaCacheModule {
   // We reissue the meta read as it sets up the mux ctrl for s2_data_muxed
   io.meta_read.valid := fire
   io.meta_read.bits.idx := req_idx
-  io.meta_read.bits.tag := req.addr_block >> UInt(idxBits)
+  io.meta_read.bits.tag := req.addr_block >> idxBits
 
   io.data_req.valid := fire
   io.data_req.bits.way_en := req.way_en
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 0346f843..1b08ce87 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -125,7 +125,7 @@ class PTW(n: Int) extends CoreModule
   val resp_err = state === s_error
   val resp_val = state === s_done || resp_err
 
-  val r_resp_ppn = io.mem.req.bits.addr >> UInt(pgIdxBits)
+  val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
   val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)
 
   for (i <- 0 until io.requestor.size) {
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 36d140a7..25df6265 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -331,7 +331,7 @@ class Rocket extends CoreModule
   // writeback arbitration
   val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
   val dmem_resp_fpu =  io.dmem.resp.bits.tag(0).toBool
-  val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt >> UInt(1)
+  val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt()(5,1)
   val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
   val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
 

From 1718333f8375e116d733a35fdb37b71039c58dde Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 5 Aug 2015 15:29:33 -0700
Subject: [PATCH 02/35] Don't use Vec as lvalue

---
 rocket/src/main/scala/fpu.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 3b5810b8..e41278b6 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -131,8 +131,10 @@ class FPUDecoder extends Module
           FSQRT_D  -> List(FCMD_SQRT,   N,Y,Y,N,N,Y,X,N,N,N,N,N,N,Y,Y,Y)
           ))
   val s = io.sigs
-  Vec(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.single, s.fromint,
-      s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.round, s.wflags) := decoder
+  val sigs = Seq(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
+                 s.swap23, s.single, s.fromint, s.toint, s.fastpipe, s.fma,
+                 s.div, s.sqrt, s.round, s.wflags)
+  sigs zip decoder map {case(s,d) => s := d}
 }
 
 class FPUIO extends Bundle {

From 78b2e947de12c30f136ac4d0c80d2870ef9a0f4d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 11 Sep 2015 15:43:07 -0700
Subject: [PATCH 03/35] Chisel3 compatibility fixes

---
 rocket/src/main/scala/arbiter.scala  |  2 +-
 rocket/src/main/scala/btb.scala      |  2 +-
 rocket/src/main/scala/csr.scala      |  4 ++--
 rocket/src/main/scala/fpu.scala      |  2 +-
 rocket/src/main/scala/icache.scala   |  9 ++++-----
 rocket/src/main/scala/nbdcache.scala | 21 ++++++++++-----------
 rocket/src/main/scala/ptw.scala      |  2 +-
 rocket/src/main/scala/rocket.scala   |  6 +++---
 8 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index 01d592a5..d995ff5f 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -8,7 +8,7 @@ import uncore._
 class HellaCacheArbiter(n: Int) extends Module
 {
   val io = new Bundle {
-    val requestor = Vec.fill(n){new HellaCacheIO}.flip
+    val requestor = Vec(new HellaCacheIO, n).flip
     val mem = new HellaCacheIO
   }
 
diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 5e0adb68..b0ab7b11 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -35,7 +35,7 @@ class RAS(nras: Int) {
 
   private val count = Reg(init=UInt(0,log2Up(nras+1)))
   private val pos = Reg(init=UInt(0,log2Up(nras)))
-  private val stack = Reg(Vec.fill(nras){UInt()})
+  private val stack = Reg(Vec(UInt(), nras))
 }
 
 class BHTResp extends Bundle with BTBParameters {
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 5a5fc3ca..d906955a 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -85,8 +85,8 @@ class CSRFileIO extends CoreBundle {
   val evec = UInt(OUTPUT, vaddrBitsExtended)
   val exception = Bool(INPUT)
   val retire = UInt(INPUT, log2Up(1+retireWidth))
-  val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
-  val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
+  val uarch_counters = Vec(UInt(INPUT, log2Up(1+retireWidth)), 16)
+  val custom_mrw_csrs = Vec(UInt(INPUT, xLen), params(NCustomMRWCSRs))
   val cause = UInt(INPUT, xLen)
   val pc = UInt(INPUT, vaddrBitsExtended)
   val fatc = Bool(OUTPUT)
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index e41278b6..ba91096f 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -456,7 +456,7 @@ class FPU extends Module
   val memLatencyMask = latencyMask(mem_ctrl, 2)
 
   val wen = Reg(init=Bits(0, maxLatency-1))
-  val winfo = Reg(Vec.fill(maxLatency-1){Bits()})
+  val winfo = Reg(Vec(Bits(), maxLatency-1))
   val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
   val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
   val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 50294282..b6ea99ff 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -21,7 +21,7 @@ class FrontendReq extends CoreBundle {
 
 class FrontendResp extends CoreBundle {
   val pc = UInt(width = vaddrBitsExtended)  // ID stage PC
-  val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
+  val data = Vec(Bits(width = coreInstBits), coreFetchWidth)
   val mask = Bits(width = coreFetchWidth)
   val xcpt_if = Bool()
 }
@@ -196,12 +196,11 @@ class ICache extends FrontendModule
 
   val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
   val entagbits = code.width(tagBits)
-  val tag_array = SeqMem(Bits(width = entagbits*nWays), nSets)
+  val tag_array = SeqMem(Vec(Bits(width = entagbits), nWays), nSets)
   val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
   when (refill_done) {
-    val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way))
     val tag = code.encode(s2_tag).toUInt
-    tag_array.write(s2_idx, Fill(nWays, tag), wmask)
+    tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
   }
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
@@ -225,7 +224,7 @@ class ICache extends FrontendModule
     val s2_vb = Reg(Bool())
     val s2_tag_disparity = Reg(Bool())
     val s2_tag_match = Reg(Bool())
-    val tag_out = tag_rdata(entagbits*(i+1)-1, entagbits*i)
+    val tag_out = tag_rdata(i)
     when (s1_valid && rdy && !stall) {
       s2_vb := s1_vb
       s2_tag_disparity := code.decode(tag_out).error
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index f58cc29e..0c3360bb 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -538,7 +538,7 @@ class DataArray extends L1HellaCacheModule {
   val io = new Bundle {
     val read = Decoupled(new L1DataReadReq).flip
     val write = Decoupled(new L1DataWriteReq).flip
-    val resp = Vec.fill(nWays){Bits(OUTPUT, encRowBits)}
+    val resp = Vec(Bits(OUTPUT, encRowBits), nWays)
   }
 
   val waddr = io.write.bits.addr >> rowOffBits
@@ -551,13 +551,12 @@ class DataArray extends L1HellaCacheModule {
       val resp = Wire(Vec(Bits(width = encRowBits), rowWords))
       val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
       for (p <- 0 until resp.size) {
-        val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
+        val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
         when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
-          val data = Fill(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
-          val mask = FillInterleaved(encDataBits, wway_en)
-          array.write(waddr, data, mask)
+          val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
+          array.write(waddr, data, wway_en.toBools)
         }
-        resp(p) := array.read(raddr, rway_en.orR && io.read.valid)
+        resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits
       }
       for (dw <- 0 until rowWords) {
         val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
@@ -568,13 +567,13 @@ class DataArray extends L1HellaCacheModule {
       }
     }
   } else {
-    val wmask = FillInterleaved(encDataBits, io.write.bits.wmask)
     for (w <- 0 until nWays) {
-      val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
+      val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
       when (io.write.bits.way_en(w) && io.write.valid) {
-        array.write(waddr, io.write.bits.data, wmask)
+        val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
+        array.write(waddr, data, io.write.bits.wmask.toBools)
       }
-      io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid)
+      io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).toBits
     }
   }
 
@@ -749,7 +748,7 @@ class HellaCache extends L1HellaCacheModule {
 
   val s2_data = Wire(Vec(Bits(width=encRowBits), nWays))
   for (w <- 0 until nWays) {
-    val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
+    val regs = Reg(Vec(Bits(width = encDataBits), rowWords))
     val en1 = s1_clk_en && s1_tag_eq_way(w)
     for (i <- 0 until regs.size) {
       val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 1b08ce87..1a49cee0 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -54,7 +54,7 @@ class PTE extends CoreBundle {
 class PTW(n: Int) extends CoreModule
 {
   val io = new Bundle {
-    val requestor = Vec.fill(n){new TLBPTWIO}.flip
+    val requestor = Vec(new TLBPTWIO, n).flip
     val mem = new HellaCacheIO
     val dpath = new DatapathPTWIO
   }
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 25df6265..d4b5984e 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -180,9 +180,9 @@ class Rocket extends CoreModule
 
   // execute stage
   val bypass_mux = Vec(bypass_sources.map(_._3))
-  val ex_reg_rs_bypass = Reg(Vec.fill(id_raddr.size)(Bool()))
-  val ex_reg_rs_lsb = Reg(Vec.fill(id_raddr.size)(Bits()))
-  val ex_reg_rs_msb = Reg(Vec.fill(id_raddr.size)(Bits()))
+  val ex_reg_rs_bypass = Reg(Vec(Bool(), id_raddr.size))
+  val ex_reg_rs_lsb = Reg(Vec(UInt(), id_raddr.size))
+  val ex_reg_rs_msb = Reg(Vec(UInt(), id_raddr.size))
   val ex_rs = for (i <- 0 until id_raddr.size)
     yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
   val ex_imm = imm(ex_ctrl.sel_imm, ex_reg_inst)

From 91458bef1c54adc0237b70073b81abc8b41b4663 Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Thu, 10 Sep 2015 18:12:23 -0700
Subject: [PATCH 04/35] [commitlog] Initial commit log for integer working

---
 rocket/src/main/scala/rocket.scala | 36 +++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index d4b5984e..4c81d8e4 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -492,12 +492,46 @@ class Rocket extends CoreModule
   io.rocc.cmd.bits.rs1 := wb_reg_wdata
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
 
-  printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
+  val COMMITLOG = true
+
+  if (COMMITLOG) {
+    val pc = Wire(SInt(width=64))
+    pc := wb_reg_pc//.toSInt()
+    val inst = wb_reg_inst
+    val rd = RegNext(RegNext(RegNext(id_waddr)))
+    val wfd = wb_ctrl.wfd
+    val wxd = wb_ctrl.wxd
+    val has_data = wb_wen && !wb_set_sboard
+
+    when (wb_valid) {
+      // TODO add privileged level
+      when (wfd) {
+        printf ("0x%x (0x%x) f%d\n", pc, inst, rd)
+      }
+      .elsewhen (wxd && rd != UInt(0) && has_data) {
+        printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)
+      }
+      .elsewhen (wxd && rd != UInt(0) && !has_data) {
+        printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd)
+      }
+      .otherwise { // !wxd || (wxd && rd == 0)
+        printf ("0x%x (0x%x)\n", pc, inst)
+      }
+    }
+
+    // ll write data
+    when (ll_wen) {
+      printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
+    }
+  }
+  else {
+    printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
          io.host.id, csr.io.time(32,0), wb_valid, wb_reg_pc,
          Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
          wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
          wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
          wb_reg_inst, wb_reg_inst)
+  }
 
   def checkExceptions(x: Seq[(Bool, UInt)]) =
     (x.map(_._1).reduce(_||_), PriorityMux(x))

From d630a0385777cad1e87b80957443f5e1bc4ecfaf Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Fri, 11 Sep 2015 03:45:31 -0700
Subject: [PATCH 05/35] [commitlog] Added FP instructions to the commitlog

---
 rocket/src/main/scala/fpu.scala    | 23 ++++++++++++++++++-----
 rocket/src/main/scala/rocket.scala | 10 +++++-----
 2 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index ba91096f..d435daca 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -353,7 +353,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
   io.out := Pipe(valid, res, latency-1)
 }
 
-class FPU extends Module
+class FPU extends CoreModule
 {
   val io = new FPUIO
 
@@ -383,7 +383,12 @@ class FPU extends Module
 
   // regfile
   val regfile = Mem(Bits(width = 65), 32)
-  when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
+  when (load_wb) { 
+    regfile(load_wb_tag) := load_wb_data_recoded 
+    if (EnableCommitLog) {
+      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
+    }
+  }
 
   val ex_ra1::ex_ra2::ex_ra3::Nil = List.fill(3)(Reg(UInt()))
   when (io.valid) {
@@ -459,7 +464,7 @@ class FPU extends Module
   val winfo = Reg(Vec(Bits(), maxLatency-1))
   val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
   val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
-  val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))
+  val mem_winfo = Cat(mem_ctrl.single, pipeid(mem_ctrl), mem_reg_inst(11,7))
 
   for (i <- 0 until maxLatency-2) {
     when (wen(i+1)) { winfo(i) := winfo(i+1) }
@@ -477,10 +482,18 @@ class FPU extends Module
   }
 
   val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
-  val wsrc = winfo(0) >> 5
+  val wsrc = (winfo(0) >> 5)(1,0) // TODO: get rid of magic number on log(num_pipes)
   val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.wdata))(wsrc))
   val wexc = Vec(pipes.map(_.wexc))(wsrc)
-  when (wen(0) || divSqrt_wen) { regfile(waddr) := wdata }
+  when (wen(0) || divSqrt_wen) { 
+    regfile(waddr) := wdata 
+    if (EnableCommitLog) {
+      val wdata_unrec_s = hardfloat.recodedFloatNToFloatN(wdata(64,0), 23, 9)
+      val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
+      val wb_single = (winfo(0) >> 5)(2) // TODO: get rid of magic numbers
+      printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32), Mux(wb_single, wdata_unrec_s, wdata_unrec_d))
+    }
+  }
 
   val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
   val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 4c81d8e4..157b55ed 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -43,6 +43,8 @@ abstract trait CoreParameters extends UsesParameters {
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
   val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
 
+  val EnableCommitLog = true
+
   if(params(FastLoadByte)) require(params(FastLoadWord))
 }
 
@@ -492,11 +494,9 @@ class Rocket extends CoreModule
   io.rocc.cmd.bits.rs1 := wb_reg_wdata
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
 
-  val COMMITLOG = true
-
-  if (COMMITLOG) {
+  if (EnableCommitLog) {
     val pc = Wire(SInt(width=64))
-    pc := wb_reg_pc//.toSInt()
+    pc := wb_reg_pc
     val inst = wb_reg_inst
     val rd = RegNext(RegNext(RegNext(id_waddr)))
     val wfd = wb_ctrl.wfd
@@ -506,7 +506,7 @@ class Rocket extends CoreModule
     when (wb_valid) {
       // TODO add privileged level
       when (wfd) {
-        printf ("0x%x (0x%x) f%d\n", pc, inst, rd)
+        printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32))
       }
       .elsewhen (wxd && rd != UInt(0) && has_data) {
         printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)

From 53a02a62c8a85fc07fb660415776212095337c4b Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Fri, 11 Sep 2015 15:48:17 -0700
Subject: [PATCH 06/35] [commitlog] Fix sp/dp bug in FPU writeback

---
 rocket/src/main/scala/fpu.scala | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index d435daca..56755e42 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -386,7 +386,7 @@ class FPU extends CoreModule
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
     if (EnableCommitLog) {
-      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
+      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever.
     }
   }
 
@@ -464,7 +464,7 @@ class FPU extends CoreModule
   val winfo = Reg(Vec(Bits(), maxLatency-1))
   val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
   val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
-  val mem_winfo = Cat(mem_ctrl.single, pipeid(mem_ctrl), mem_reg_inst(11,7))
+  val mem_winfo = Cat(pipeid(mem_ctrl), mem_ctrl.single, mem_reg_inst(11,7)) //single only used for debugging
 
   for (i <- 0 until maxLatency-2) {
     when (wen(i+1)) { winfo(i) := winfo(i+1) }
@@ -482,16 +482,17 @@ class FPU extends CoreModule
   }
 
   val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
-  val wsrc = (winfo(0) >> 5)(1,0) // TODO: get rid of magic number on log(num_pipes)
+  val wsrc = (winfo(0) >> 6)
   val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.wdata))(wsrc))
   val wexc = Vec(pipes.map(_.wexc))(wsrc)
-  when (wen(0) || divSqrt_wen) { 
+  when (wen(0) || divSqrt_wen) {
     regfile(waddr) := wdata 
     if (EnableCommitLog) {
       val wdata_unrec_s = hardfloat.recodedFloatNToFloatN(wdata(64,0), 23, 9)
       val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
-      val wb_single = (winfo(0) >> 5)(2) // TODO: get rid of magic numbers
-      printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32), Mux(wb_single, wdata_unrec_s, wdata_unrec_d))
+      val wb_single = (winfo(0) >> 5)(0)
+      printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32),
+        Mux(wb_single, Cat(Fill(32, wdata_unrec_s(31)), wdata_unrec_s), wdata_unrec_d))
     }
   }
 

From 7d14abf26215563b32898acb6729b21fab083f42 Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Fri, 11 Sep 2015 16:08:12 -0700
Subject: [PATCH 07/35] [commitlog] Added privilege-level to output

---
 rocket/src/main/scala/fpu.scala    |  2 +-
 rocket/src/main/scala/rocket.scala | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 56755e42..ede8679c 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -386,7 +386,7 @@ class FPU extends CoreModule
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
     if (EnableCommitLog) {
-      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever.
+      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
     }
   }
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 157b55ed..a04a64e6 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -502,20 +502,20 @@ class Rocket extends CoreModule
     val wfd = wb_ctrl.wfd
     val wxd = wb_ctrl.wxd
     val has_data = wb_wen && !wb_set_sboard
+    val priv = csr.io.status.prv
 
     when (wb_valid) {
-      // TODO add privileged level
       when (wfd) {
-        printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32))
+        printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32))
       }
       .elsewhen (wxd && rd != UInt(0) && has_data) {
-        printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)
+        printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata)
       }
       .elsewhen (wxd && rd != UInt(0) && !has_data) {
-        printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd)
+        printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
       }
       .otherwise { // !wxd || (wxd && rd == 0)
-        printf ("0x%x (0x%x)\n", pc, inst)
+        printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
       }
     }
 

From e22bf02a80cd091f7b9a4cc4eeedeb1597bfa64e Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Fri, 11 Sep 2015 23:08:23 -0700
Subject: [PATCH 08/35] [commitlog] CSR's cycle optionally set to instret

  - Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
---
 rocket/src/main/scala/csr.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index d906955a..95f33aaf 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -123,8 +123,8 @@ class CSRFile extends CoreModule
   val reg_fromhost = Reg(init=Bits(0, xLen))
   val reg_stats = Reg(init=Bool(false))
   val reg_time = Reg(UInt(width = xLen))
-  val reg_cycle = WideCounter(xLen)
   val reg_instret = WideCounter(xLen, io.retire)
+  val reg_cycle = if (EnableCommitLog) { reg_instret } else { WideCounter(xLen) }
   val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))

From 3b48d8569cb27e0b35d42a37795a35c1f188f875 Mon Sep 17 00:00:00 2001
From: Scott Beamer <sbeamer@eecs.berkeley.edu>
Date: Mon, 14 Sep 2015 14:32:24 -0700
Subject: [PATCH 09/35] [commitlog] don't print out writebacks to x0

---
 rocket/src/main/scala/rocket.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index a04a64e6..8b6e3e8f 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -520,7 +520,7 @@ class Rocket extends CoreModule
     }
 
     // ll write data
-    when (ll_wen) {
+    when (ll_wen && rf_waddr != UInt(0)) {
       printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
     }
   }

From 76bf1da3109fb3dd11e53d3c84a2d1b7636a211e Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Tue, 15 Sep 2015 15:53:36 -0700
Subject: [PATCH 10/35] [commitlog] zero-extend SP write-back values

---
 rocket/src/main/scala/fpu.scala    | 5 +++--
 rocket/src/main/scala/rocket.scala | 7 ++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index ede8679c..15ee0920 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -386,7 +386,8 @@ class FPU extends CoreModule
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
     if (EnableCommitLog) {
-      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
+      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32),
+        Mux(load_wb_single, load_wb_data(31,0), load_wb_data))
     }
   }
 
@@ -492,7 +493,7 @@ class FPU extends CoreModule
       val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
       val wb_single = (winfo(0) >> 5)(0)
       printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32),
-        Mux(wb_single, Cat(Fill(32, wdata_unrec_s(31)), wdata_unrec_s), wdata_unrec_d))
+        Mux(wb_single, Cat(UInt(0,32), wdata_unrec_s), wdata_unrec_d))
     }
   }
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 8b6e3e8f..9a336705 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -43,7 +43,9 @@ abstract trait CoreParameters extends UsesParameters {
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
   val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
 
-  val EnableCommitLog = true
+  // Print out log of committed instructions and their writeback values.
+  // Requires post-processing due to out-of-order writebacks.
+  val EnableCommitLog = false
 
   if(params(FastLoadByte)) require(params(FastLoadWord))
 }
@@ -514,12 +516,11 @@ class Rocket extends CoreModule
       .elsewhen (wxd && rd != UInt(0) && !has_data) {
         printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
       }
-      .otherwise { // !wxd || (wxd && rd == 0)
+      .otherwise {
         printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
       }
     }
 
-    // ll write data
     when (ll_wen && rf_waddr != UInt(0)) {
       printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
     }

From e72e5a34b561bc6065698ae9814a99151a673401 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 21 Sep 2015 12:17:46 -0700
Subject: [PATCH 11/35] Fix storage of SP values in DP registers

The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
---
 rocket/src/main/scala/fpu.scala | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 15ee0920..10d657a2 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -348,7 +348,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
   fma.io.c := in.in3
 
   val res = Wire(new FPResult)
-  res.data := fma.io.out
+  res.data := Cat(SInt(-1, 32), fma.io.out)
   res.exc := fma.io.exceptionFlags
   io.out := Pipe(valid, res, latency-1)
 }
@@ -447,12 +447,12 @@ class FPU extends CoreModule
   val divSqrt_in_flight = Reg(init=Bool(false))
 
   // writeback arbitration
-  case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: UInt, wexc: UInt)
+  case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
   val pipes = List(
-    Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc),
-    Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc),
-    Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, Cat(SInt(-1, 32), sfma.io.out.bits.data), sfma.io.out.bits.exc),
-    Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits.data, dfma.io.out.bits.exc))
+    Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
+    Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
+    Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out.bits),
+    Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits))
   def latencyMask(c: FPUCtrlSigs, offset: Int) = {
     require(pipes.forall(_.lat >= offset))
     pipes.map(p => Mux(p.cond(c), UInt(1 << p.lat-offset), UInt(0))).reduce(_|_)
@@ -484,8 +484,8 @@ class FPU extends CoreModule
 
   val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
   val wsrc = (winfo(0) >> 6)
-  val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.wdata))(wsrc))
-  val wexc = Vec(pipes.map(_.wexc))(wsrc)
+  val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.res.data))(wsrc))
+  val wexc = Vec(pipes.map(_.res.exc))(wsrc)
   when (wen(0) || divSqrt_wen) {
     regfile(waddr) := wdata 
     if (EnableCommitLog) {

From 382faba4a68a5b008df456026dea6e69bb8c2347 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 5 Aug 2015 11:01:01 -0700
Subject: [PATCH 12/35] Implement bypassing L1 data cache for MMIO

---
 rocket/src/main/scala/nbdcache.scala | 159 ++++++++++++++++++++++++---
 1 file changed, 145 insertions(+), 14 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 0c3360bb..fe712f05 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -4,18 +4,23 @@ package rocket
 
 import Chisel._
 import uncore._
+import junctions.MMIOBase
 import Util._
 
 case object WordBits extends Field[Int]
 case object StoreDataQueueDepth extends Field[Int]
 case object ReplayQueueDepth extends Field[Int]
 case object NMSHRs extends Field[Int]
+case object NIOMSHRs extends Field[Int]
 case object LRSCCycles extends Field[Int]
 
 abstract trait L1HellaCacheParameters extends L1CacheParameters {
   val wordBits = params(WordBits)
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
+  val beatBytes = params(CacheBlockBytes) / params(TLDataBeats)
+  val beatWords = beatBytes / wordBytes
+  val beatOffBits = log2Up(beatBytes)
   val idxMSB = untagBits-1
   val idxLSB = blockOffBits
   val offsetmsb = idxLSB-1
@@ -26,6 +31,8 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
   val encRowBits = encDataBits*rowWords
   val sdqDepth = params(StoreDataQueueDepth)
   val nMSHRs = params(NMSHRs)
+  val nIOMSHRs = params(NIOMSHRs)
+  val mmioBase = params(MMIOBase)
 }
 
 abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
@@ -130,6 +137,83 @@ class WritebackReq extends Release with CacheParameters {
   val way_en = Bits(width = nWays)
 }
 
+class IOMSHR(id: Int) extends L1HellaCacheModule {
+  val io = new Bundle {
+    val req = Decoupled(new HellaCacheReq).flip
+    val acquire = Decoupled(new Acquire)
+    val grant = Valid(new Grant).flip
+    val resp = Decoupled(new HellaCacheResp)
+  }
+
+  def wordFromBeat(addr: UInt, dat: UInt) = {
+    val offset = addr(beatOffBits - 1, wordOffBits)
+    val shift = Cat(offset, UInt(0, wordOffBits + 3))
+    (dat >> shift)(wordBits - 1, 0)
+  }
+
+  val req = Reg(new HellaCacheReq)
+  val grant_word = Reg(UInt(width = wordBits))
+
+  val storegen = new StoreGen(req.typ, req.addr, req.data)
+  val loadgen = new LoadGen(req.typ, req.addr, grant_word, Bool(false))
+
+  val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
+  val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
+  val beat_data = Fill(beatWords, storegen.data)
+
+  val addr_byte = req.addr(beatOffBits - 1, 0)
+  val a_type = Mux(isRead(req.cmd), Acquire.getType, Acquire.putType)
+  val union = Mux(isRead(req.cmd),
+    Cat(addr_byte, req.typ, M_XRD), beat_mask)
+
+  val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4)
+  val state = Reg(init = s_idle)
+
+  io.req.ready := (state === s_idle)
+
+  io.acquire.valid := (state === s_acquire)
+  io.acquire.bits := Acquire(
+    is_builtin_type = Bool(true),
+    a_type = a_type,
+    client_xact_id = UInt(id),
+    addr_block = req.addr(paddrBits - 1, blockOffBits),
+    addr_beat = req.addr(blockOffBits - 1, beatOffBits),
+    data = beat_data,
+    // alloc bit should always be false
+    union = Cat(union, Bool(false)))
+
+  io.resp.valid := (state === s_resp)
+  io.resp.bits := req
+  io.resp.bits.has_data := isRead(req.cmd)
+  io.resp.bits.data := loadgen.word
+  io.resp.bits.data_subword := loadgen.byte
+  io.resp.bits.store_data := req.data
+  io.resp.bits.nack := Bool(false)
+  io.resp.bits.replay := io.resp.valid
+
+  when (io.req.fire()) {
+    req := io.req.bits
+    state := s_acquire
+  }
+
+  when (io.acquire.fire()) {
+    state := s_grant
+  }
+
+  when (state === s_grant && io.grant.valid) {
+    when (isRead(req.cmd)) {
+      grant_word := wordFromBeat(req.addr, io.grant.bits.data)
+      state := s_resp
+    } .otherwise {
+      state := s_idle
+    }
+  }
+
+  when (io.resp.fire()) {
+    state := s_idle
+  }
+}
+
 class MSHR(id: Int) extends L1HellaCacheModule {
   val io = new Bundle {
     val req_pri_val    = Bool(INPUT)
@@ -282,6 +366,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
 class MSHRFile extends L1HellaCacheModule {
   val io = new Bundle {
     val req = Decoupled(new MSHRReq).flip
+    val resp = Decoupled(new HellaCacheResp)
     val secondary_miss = Bool(OUTPUT)
 
     val mem_req  = Decoupled(new Acquire)
@@ -296,10 +381,13 @@ class MSHRFile extends L1HellaCacheModule {
     val fence_rdy = Bool(OUTPUT)
   }
 
+  // determine if the request is in the memory region or mmio region
+  val cacheable = io.req.bits.addr < UInt(mmioBase)
+
   val sdq_val = Reg(init=Bits(0, sdqDepth))
   val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
   val sdq_rdy = !sdq_val.andR
-  val sdq_enq = io.req.valid && io.req.ready && isWrite(io.req.bits.cmd)
+  val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
   val sdq = Mem(io.req.bits.data, sdqDepth)
   when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
 
@@ -313,7 +401,7 @@ class MSHRFile extends L1HellaCacheModule {
   val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
   val mem_req_arb = Module(new LockingArbiter(
                                   new Acquire,
-                                  nMSHRs,
+                                  nMSHRs + nIOMSHRs,
                                   outerDataBeats,
                                   (a: Acquire) => a.hasMultibeatData()))
   val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
@@ -360,14 +448,44 @@ class MSHRFile extends L1HellaCacheModule {
     when (!mshr.io.probe_rdy) { io.probe_rdy := false }
   }
 
-  alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
+  alloc_arb.io.out.ready := io.req.valid && sdq_rdy && cacheable && !idx_match
 
   io.meta_read <> meta_read_arb.io.out
   io.meta_write <> meta_write_arb.io.out
   io.mem_req <> mem_req_arb.io.out
   io.wb_req <> wb_req_arb.io.out
 
-  io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
+  val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
+  val resp_arb = Module(new Arbiter(new HellaCacheResp, nIOMSHRs))
+
+  var mmio_rdy = Bool(false)
+
+  for (i <- 0 until nIOMSHRs) {
+    val id = nMSHRs + i
+    val mshr = Module(new IOMSHR(id))
+
+    mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
+    mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
+    mshr.io.req.bits := io.req.bits
+
+    mmio_rdy = mmio_rdy || mshr.io.req.ready
+
+    mem_req_arb.io.in(id) <> mshr.io.acquire
+
+    mshr.io.grant.bits := io.mem_grant.bits
+    mshr.io.grant.valid := io.mem_grant.valid &&
+        io.mem_grant.bits.client_xact_id === UInt(id)
+
+    resp_arb.io.in(i) <> mshr.io.resp
+
+    when (!mshr.io.req.ready) { io.fence_rdy := Bool(false) }
+  }
+
+  mmio_alloc_arb.io.out.ready := io.req.valid && !cacheable
+
+  io.resp <> resp_arb.io.out
+  io.req.ready := Mux(!cacheable, mmio_rdy,
+    Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy)
   io.secondary_miss := idx_match
   io.refill := refillMux(io.mem_grant.bits.client_xact_id)
 
@@ -824,7 +942,11 @@ class HellaCache extends L1HellaCacheModule {
   mshrs.io.mem_grant.valid := narrow_grant.fire()
   mshrs.io.mem_grant.bits := narrow_grant.bits
   narrow_grant.ready := writeArb.io.in(1).ready || !narrow_grant.bits.hasData()
-  writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData()
+  /* The last clause here is necessary in order to prevent the responses for
+   * the IOMSHRs from being written into the data array. It works because the
+   * IOMSHR ids start right the ones for the regular MSHRs. */
+  writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData() &&
+                             narrow_grant.bits.client_xact_id < UInt(nMSHRs)
   writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
   writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
   writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
@@ -893,16 +1015,25 @@ class HellaCache extends L1HellaCacheModule {
     io.cpu.req.ready := Bool(false)
   }
 
-  io.cpu.resp.valid  := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
-  io.cpu.resp.bits.nack := s2_valid && s2_nack
-  io.cpu.resp.bits := s2_req
-  io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
-  io.cpu.resp.bits.replay := s2_replay
-  io.cpu.resp.bits.data := loadgen.word
-  io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
-  io.cpu.resp.bits.store_data := s2_req.data
-  io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
+  val cache_resp = Wire(Valid(new HellaCacheResp))
+  cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
+  cache_resp.bits := s2_req
+  cache_resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
+  cache_resp.bits.data := loadgen.word
+  cache_resp.bits.data_subword := loadgen.byte | s2_sc_fail
+  cache_resp.bits.store_data := s2_req.data
+  cache_resp.bits.nack := s2_valid && s2_nack
+  cache_resp.bits.replay := s2_replay
 
+  val uncache_resp = Wire(Valid(new HellaCacheResp))
+  uncache_resp.bits := mshrs.io.resp.bits
+  uncache_resp.valid := mshrs.io.resp.valid
+
+  val cache_pass = s2_valid || s2_replay
+  mshrs.io.resp.ready := !cache_pass
+
+  io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
+  io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
   io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
   io.cpu.replay_next.bits := s1_req.tag
 }

From d89bcd3922aac84185bac188f6bc02bb0a0ebf54 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 12 Aug 2015 21:22:54 -0700
Subject: [PATCH 13/35] modify csr file to bring in line with HTIF changes

---
 rocket/src/main/scala/csr.scala | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 95f33aaf..fca520e0 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -156,21 +156,21 @@ class CSRFile extends CoreModule
   val host_pcr_req_valid = Reg(Bool()) // don't reset
   val host_pcr_req_fire = host_pcr_req_valid && !cpu_ren
   val host_pcr_rep_valid = Reg(Bool()) // don't reset
-  val host_pcr_bits = Reg(io.host.pcr_req.bits)
-  io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
-  io.host.pcr_rep.valid := host_pcr_rep_valid
-  io.host.pcr_rep.bits := host_pcr_bits.data
-  when (io.host.pcr_req.fire()) {
+  val host_pcr_bits = Reg(io.host.pcr.req.bits)
+  io.host.pcr.req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
+  io.host.pcr.resp.valid := host_pcr_rep_valid
+  io.host.pcr.resp.bits := host_pcr_bits.data
+  when (io.host.pcr.req.fire()) {
     host_pcr_req_valid := true
-    host_pcr_bits := io.host.pcr_req.bits
+    host_pcr_bits := io.host.pcr.req.bits
   }
   when (host_pcr_req_fire) {
     host_pcr_req_valid := false
     host_pcr_rep_valid := true
     host_pcr_bits.data := io.rw.rdata
   }
-  when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
-  
+  when (io.host.pcr.resp.fire()) { host_pcr_rep_valid := false }
+
   io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
 
   val read_mstatus = io.status.toBits
@@ -411,7 +411,7 @@ class CSRFile extends CoreModule
     when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
     when (decoded_addr(CSRs.instretw)) { reg_instret := wdata }
     when (decoded_addr(CSRs.mtimecmp)) { reg_mtimecmp := wdata; reg_mip.mtip := false }
-    when (decoded_addr(CSRs.mreset) /* XXX used by HTIF to write mtime */) { reg_time := wdata }
+    when (decoded_addr(CSRs.mtime))    { reg_time := wdata }
     when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
     when (decoded_addr(CSRs.mtohost))  { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
     when (decoded_addr(CSRs.stats))    { reg_stats := wdata(0) }

From 16c748576a9c18b2b353c02b80deca2a922eba70 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 10 Sep 2015 17:57:03 -0700
Subject: [PATCH 14/35] don't mux data_word_bypass between IOMSHR and cache

---
 rocket/src/main/scala/nbdcache.scala | 9 ++++-----
 rocket/src/main/scala/rocket.scala   | 8 ++++----
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index fe712f05..1a401f0f 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -70,7 +70,7 @@ class HellaCacheResp extends HasCoreMemOp with HasCoreData {
   val nack = Bool() // comes 2 cycles after req.fire
   val replay = Bool()
   val has_data = Bool()
-  val data_subword = Bits(width = coreDataBits)
+  val data_word_bypass = Bits(width = coreDataBits)
   val store_data = Bits(width = coreDataBits)
 }
 
@@ -185,8 +185,7 @@ class IOMSHR(id: Int) extends L1HellaCacheModule {
   io.resp.valid := (state === s_resp)
   io.resp.bits := req
   io.resp.bits.has_data := isRead(req.cmd)
-  io.resp.bits.data := loadgen.word
-  io.resp.bits.data_subword := loadgen.byte
+  io.resp.bits.data := loadgen.byte
   io.resp.bits.store_data := req.data
   io.resp.bits.nack := Bool(false)
   io.resp.bits.replay := io.resp.valid
@@ -1019,8 +1018,7 @@ class HellaCache extends L1HellaCacheModule {
   cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
   cache_resp.bits := s2_req
   cache_resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
-  cache_resp.bits.data := loadgen.word
-  cache_resp.bits.data_subword := loadgen.byte | s2_sc_fail
+  cache_resp.bits.data := loadgen.byte | s2_sc_fail
   cache_resp.bits.store_data := s2_req.data
   cache_resp.bits.nack := s2_valid && s2_nack
   cache_resp.bits.replay := s2_replay
@@ -1033,6 +1031,7 @@ class HellaCache extends L1HellaCacheModule {
   mshrs.io.resp.ready := !cache_pass
 
   io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
+  io.cpu.resp.bits.data_word_bypass := loadgen.word
   io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
   io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
   io.cpu.replay_next.bits := s1_req.tag
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 9a336705..cead7ad2 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -167,8 +167,8 @@ class Rocket extends CoreModule
     (id_illegal_insn,           UInt(Causes.illegal_instruction))))
 
   val dcache_bypass_data =
-    if(params(FastLoadByte)) io.dmem.resp.bits.data_subword
-    else if(params(FastLoadWord)) io.dmem.resp.bits.data
+    if(params(FastLoadByte)) io.dmem.resp.bits.data
+    else if(params(FastLoadWord)) io.dmem.resp.bits.data_word_bypass
     else wb_reg_wdata
 
   // detect bypass opportunities
@@ -364,7 +364,7 @@ class Rocket extends CoreModule
   val wb_wen = wb_valid && wb_ctrl.wxd
   val rf_wen = wb_wen || ll_wen 
   val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
-  val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword,
+  val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
                  Mux(ll_wen, ll_wdata,
                  Mux(wb_ctrl.csr != CSR.N, csr.io.rw.rdata,
                  wb_reg_wdata)))
@@ -474,7 +474,7 @@ class Rocket extends CoreModule
   io.fpu.inst := id_inst
   io.fpu.fromint_data := ex_rs(0)
   io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
-  io.fpu.dmem_resp_data := io.dmem.resp.bits.data
+  io.fpu.dmem_resp_data := io.dmem.resp.bits.data_word_bypass
   io.fpu.dmem_resp_type := io.dmem.resp.bits.typ
   io.fpu.dmem_resp_tag := dmem_resp_waddr
 

From 9eb988a4c6bad33ede6106cbd76b0e826a13ece1 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 22 Sep 2015 09:42:27 -0700
Subject: [PATCH 15/35] make sure access to invalid physical address treated as
 exception

---
 rocket/src/main/scala/icache.scala   |  4 +++-
 rocket/src/main/scala/nbdcache.scala |  5 ++---
 rocket/src/main/scala/rocket.scala   |  1 +
 rocket/src/main/scala/tlb.scala      | 16 +++++++++++-----
 4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index b6ea99ff..f9650b95 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -106,7 +106,9 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
   icache.io.req.bits.idx := io.cpu.npc
   icache.io.invalidate := io.cpu.invalidate
   icache.io.req.bits.ppn := tlb.io.resp.ppn
-  icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
+  icache.io.req.bits.kill := io.cpu.req.valid ||
+    tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
+    icmiss || io.ptw.invalidate
   icache.io.resp.ready := !stall && !s1_same_block
 
   io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 1a401f0f..b7aff715 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -32,7 +32,6 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
   val sdqDepth = params(StoreDataQueueDepth)
   val nMSHRs = params(NMSHRs)
   val nIOMSHRs = params(NIOMSHRs)
-  val mmioBase = params(MMIOBase)
 }
 
 abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
@@ -788,8 +787,8 @@ class HellaCache extends L1HellaCacheModule {
     
   io.cpu.xcpt.ma.ld := s1_read && misaligned
   io.cpu.xcpt.ma.st := s1_write && misaligned
-  io.cpu.xcpt.pf.ld := !s1_req.phys && s1_read && dtlb.io.resp.xcpt_ld
-  io.cpu.xcpt.pf.st := !s1_req.phys && s1_write && dtlb.io.resp.xcpt_st
+  io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
+  io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
 
   assert (!(Reg(next=
     (io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index cead7ad2..f8d9e862 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -42,6 +42,7 @@ abstract trait CoreParameters extends UsesParameters {
   val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
   val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
+  val mmioBase = params(MMIOBase)
 
   // Print out log of committed instructions and their writeback values.
   // Requires post-processing due to out-of-order writebacks.
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 87569e10..16f370f3 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -157,20 +157,26 @@ class TLB extends TLBModule {
 
   val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm
   val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
+  val bad_pa = !vm_enabled && io.req.bits.vpn >= UInt(mmioBase >> vpnBits)
   // it's only a store hit if the dirty bit is set
   val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
   val tag_hit = tag_hits.orR
   val tlb_hit = vm_enabled && tag_hit
   val tlb_miss = vm_enabled && !tag_hit && !bad_va
-  
+
   when (io.req.valid && tlb_hit) {
     plru.access(OHToUInt(tag_cam.io.hits))
   }
 
+  val addrMap = params(NASTIAddrHashMap)
+  val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits))
+  val addr_ok = addrMap.isValid(paddr)
+  val addr_prot = addrMap.getProt(paddr)
+
   io.req.ready := state === s_ready
-  io.resp.xcpt_ld := bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
-  io.resp.xcpt_st := bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
-  io.resp.xcpt_if := bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
+  io.resp.xcpt_ld := !addr_ok || !addr_prot.r || bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
+  io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
+  io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
   io.resp.miss := tlb_miss
   io.resp.ppn := Mux(vm_enabled && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
   io.resp.hit_idx := tag_cam.io.hits
@@ -186,7 +192,7 @@ class TLB extends TLBModule {
   io.ptw.req.bits.store := r_req.store
   io.ptw.req.bits.fetch := r_req.instruction
 
-  when (io.req.fire() && tlb_miss) {
+  when (io.req.fire() && tlb_miss && addr_ok) {
     state := s_request
     r_refill_tag := lookup_tag
     r_refill_waddr := repl_waddr

From a66bdb19566b4c6ab33360c43adff9fe63a079b2 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 24 Sep 2015 17:53:26 -0700
Subject: [PATCH 16/35] replace remaining uses of Vec.fill

---
 rocket/src/main/scala/icache.scala   | 2 +-
 rocket/src/main/scala/nbdcache.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index f9650b95..65305f00 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -202,7 +202,7 @@ class ICache extends FrontendModule
   val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
   when (refill_done) {
     val tag = code.encode(s2_tag).toUInt
-    tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
+    tag_array.write(s2_idx, Vec(nWays, tag), Vec.tabulate(nWays)(repl_way === _))
   }
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index b7aff715..c4b246e9 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -669,7 +669,7 @@ class DataArray extends L1HellaCacheModule {
       for (p <- 0 until resp.size) {
         val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
         when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
-          val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
+          val data = Vec(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
           array.write(waddr, data, wway_en.toBools)
         }
         resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits

From 0bfb2962a63e8be9b09b0770257b1ce841214550 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 25 Sep 2015 15:26:11 -0700
Subject: [PATCH 17/35] Assume coh.isRead returns true for store-conditional

This requires an uncore update.
---
 rocket/src/main/scala/nbdcache.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index c4b246e9..9596008d 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -151,10 +151,11 @@ class IOMSHR(id: Int) extends L1HellaCacheModule {
   }
 
   val req = Reg(new HellaCacheReq)
+  val req_cmd_sc = req.cmd === M_XSC
   val grant_word = Reg(UInt(width = wordBits))
 
   val storegen = new StoreGen(req.typ, req.addr, req.data)
-  val loadgen = new LoadGen(req.typ, req.addr, grant_word, Bool(false))
+  val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc)
 
   val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
   val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
@@ -184,7 +185,7 @@ class IOMSHR(id: Int) extends L1HellaCacheModule {
   io.resp.valid := (state === s_resp)
   io.resp.bits := req
   io.resp.bits.has_data := isRead(req.cmd)
-  io.resp.bits.data := loadgen.byte
+  io.resp.bits.data := loadgen.byte | req_cmd_sc
   io.resp.bits.store_data := req.data
   io.resp.bits.nack := Bool(false)
   io.resp.bits.replay := io.resp.valid
@@ -735,7 +736,6 @@ class HellaCache extends L1HellaCacheModule {
   val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)
   val s1_read  = isRead(s1_req.cmd)
   val s1_write = isWrite(s1_req.cmd)
-  val s1_sc = s1_req.cmd === M_XSC
   val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
 
   val dtlb = Module(new TLB)
@@ -1032,7 +1032,7 @@ class HellaCache extends L1HellaCacheModule {
   io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
   io.cpu.resp.bits.data_word_bypass := loadgen.word
   io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
-  io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
+  io.cpu.replay_next.valid := s1_replay && s1_read
   io.cpu.replay_next.bits := s1_req.tag
 }
 

From c3fff12ff02e5c67e6d1c6b7b8348d8fda46ca51 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 25 Sep 2015 17:02:51 -0700
Subject: [PATCH 18/35] Revert "replace remaining uses of Vec.fill"

This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
---
 rocket/src/main/scala/icache.scala   | 2 +-
 rocket/src/main/scala/nbdcache.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 65305f00..f9650b95 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -202,7 +202,7 @@ class ICache extends FrontendModule
   val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
   when (refill_done) {
     val tag = code.encode(s2_tag).toUInt
-    tag_array.write(s2_idx, Vec(nWays, tag), Vec.tabulate(nWays)(repl_way === _))
+    tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
   }
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 9596008d..a0bafb0a 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -670,7 +670,7 @@ class DataArray extends L1HellaCacheModule {
       for (p <- 0 until resp.size) {
         val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
         when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
-          val data = Vec(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
+          val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
           array.write(waddr, data, wway_en.toBools)
         }
         resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits

From 6bf8f41cef5fba4baa9ba13942668ade2d06ca20 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Sat, 26 Sep 2015 20:29:51 -0700
Subject: [PATCH 19/35] make sure passthrough requests are treated as
 vm_enabled = false

---
 rocket/src/main/scala/tlb.scala | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 16f370f3..1be0f2f0 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -155,9 +155,8 @@ class TLB extends TLBModule {
   val w_array = Mux(priv_s, sw_array.toBits, uw_array.toBits)
   val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
 
-  val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm
+  val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
   val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
-  val bad_pa = !vm_enabled && io.req.bits.vpn >= UInt(mmioBase >> vpnBits)
   // it's only a store hit if the dirty bit is set
   val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
   val tag_hit = tag_hits.orR
@@ -178,7 +177,7 @@ class TLB extends TLBModule {
   io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
   io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
   io.resp.miss := tlb_miss
-  io.resp.ppn := Mux(vm_enabled && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
+  io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
   io.resp.hit_idx := tag_cam.io.hits
 
   // clear invalid entries on access, or all entries on a TLB flush

From 4bda6b67575e0461721f55b328ae913fb53ee382 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Sat, 26 Sep 2015 21:27:36 -0700
Subject: [PATCH 20/35] fix bug in tlb refill

---
 rocket/src/main/scala/tlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 1be0f2f0..ce02f8ee 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -191,7 +191,7 @@ class TLB extends TLBModule {
   io.ptw.req.bits.store := r_req.store
   io.ptw.req.bits.fetch := r_req.instruction
 
-  when (io.req.fire() && tlb_miss && addr_ok) {
+  when (io.req.fire() && tlb_miss) {
     state := s_request
     r_refill_tag := lookup_tag
     r_refill_waddr := repl_waddr

From b93a94597c47350487d4d32a08ea30f6e1f581fd Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sun, 27 Sep 2015 13:31:52 -0700
Subject: [PATCH 21/35] Remove needless control logic

---
 rocket/src/main/scala/nbdcache.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index a0bafb0a..d2fd5c1a 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -1016,7 +1016,7 @@ class HellaCache extends L1HellaCacheModule {
   val cache_resp = Wire(Valid(new HellaCacheResp))
   cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
   cache_resp.bits := s2_req
-  cache_resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
+  cache_resp.bits.has_data := isRead(s2_req.cmd)
   cache_resp.bits.data := loadgen.byte | s2_sc_fail
   cache_resp.bits.store_data := s2_req.data
   cache_resp.bits.nack := s2_valid && s2_nack

From 5e88ead984e463c8b19408b300b7dbaed5ea86ed Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 28 Sep 2015 11:52:27 -0700
Subject: [PATCH 22/35] Add pseudo-ops to instructions.scala

---
 rocket/src/main/scala/instructions.scala | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala
index f007ebc4..b5ab974f 100644
--- a/rocket/src/main/scala/instructions.scala
+++ b/rocket/src/main/scala/instructions.scala
@@ -192,6 +192,26 @@ object Instructions {
   def CUSTOM3_RD         = BitPat("b?????????????????100?????1111011")
   def CUSTOM3_RD_RS1     = BitPat("b?????????????????110?????1111011")
   def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011")
+  def SLLI_RV32          = BitPat("b0000000??????????001?????0010011")
+  def SRLI_RV32          = BitPat("b0000000??????????101?????0010011")
+  def SRAI_RV32          = BitPat("b0100000??????????101?????0010011")
+  def FRFLAGS            = BitPat("b00000000000100000010?????1110011")
+  def FSFLAGS            = BitPat("b000000000001?????001?????1110011")
+  def FSFLAGSI           = BitPat("b000000000001?????101?????1110011")
+  def FRRM               = BitPat("b00000000001000000010?????1110011")
+  def FSRM               = BitPat("b000000000010?????001?????1110011")
+  def FSRMI              = BitPat("b000000000010?????101?????1110011")
+  def FSCSR              = BitPat("b000000000011?????001?????1110011")
+  def FRCSR              = BitPat("b00000000001100000010?????1110011")
+  def RDCYCLE            = BitPat("b11000000000000000010?????1110011")
+  def RDTIME             = BitPat("b11000000000100000010?????1110011")
+  def RDINSTRET          = BitPat("b11000000001000000010?????1110011")
+  def RDCYCLEH           = BitPat("b11001000000000000010?????1110011")
+  def RDTIMEH            = BitPat("b11001000000100000010?????1110011")
+  def RDINSTRETH         = BitPat("b11001000001000000010?????1110011")
+  def ECALL              = BitPat("b00000000000000000000000001110011")
+  def EBREAK             = BitPat("b00000000000100000000000001110011")
+  def ERET               = BitPat("b00010000000000000000000001110011")
 }
 object Causes {
   val misaligned_fetch = 0x0

From f8a7a806445ef1e41d0072c7059aea7e8a13711d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 28 Sep 2015 13:55:23 -0700
Subject: [PATCH 23/35] Make perf counters optional

---
 rocket/src/main/scala/csr.scala    | 29 +++++++++++++++++------------
 rocket/src/main/scala/rocket.scala |  1 +
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index fca520e0..6b7f6b79 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -173,6 +173,7 @@ class CSRFile extends CoreModule
 
   io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
 
+  val read_time = if (params(UsePerfCounters)) reg_time else (reg_cycle: UInt)
   val read_mstatus = io.status.toBits
   val isa_string = "IMA" +
     (if (params(UseVM)) "S" else "") +
@@ -188,13 +189,11 @@ class CSRFile extends CoreModule
     CSRs.fcsr -> (if (!params(BuildFPU).isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
     CSRs.cycle -> reg_cycle,
     CSRs.cyclew -> reg_cycle,
-    CSRs.instret -> reg_instret,
-    CSRs.instretw -> reg_instret,
-    CSRs.time -> reg_time,
-    CSRs.timew -> reg_time,
-    CSRs.stime -> reg_time,
-    CSRs.stimew -> reg_time,
-    CSRs.mtime -> reg_time,
+    CSRs.time -> read_time,
+    CSRs.timew -> read_time,
+    CSRs.stime -> read_time,
+    CSRs.stimew -> read_time,
+    CSRs.mtime -> read_time,
     CSRs.mcpuid -> UInt(cpuid),
     CSRs.mimpid -> UInt(impid),
     CSRs.mstatus -> read_mstatus,
@@ -214,6 +213,14 @@ class CSRFile extends CoreModule
     CSRs.mtohost -> reg_tohost,
     CSRs.mfromhost -> reg_fromhost)
 
+  if (params(UsePerfCounters)) {
+    read_mapping += CSRs.instret -> reg_instret
+    read_mapping += CSRs.instretw -> reg_instret
+
+    for (i <- 0 until reg_uarch_counters.size)
+      read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
+  }
+
   if (params(UseVM)) {
     val read_sstatus = Wire(init=new SStatus().fromBits(read_mstatus))
     read_sstatus.zero1 := 0
@@ -241,9 +248,6 @@ class CSRFile extends CoreModule
     read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
   }
 
-  for (i <- 0 until reg_uarch_counters.size)
-    read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
-
   for (i <- 0 until params(NCustomMRWCSRs)) {
     val addr = 0x790 + i // turn 0x790 into parameter CustomMRWCSRBase?
     require(addr >= 0x780 && addr <= 0x7ff, "custom MRW CSR address " + i + " is out of range")
@@ -341,7 +345,7 @@ class CSRFile extends CoreModule
 
   assert(PopCount(insn_ret :: insn_redirect_trap :: io.exception :: csr_xcpt :: io.csr_replay :: Nil) <= 1, "these conditions must be mutually exclusive")
 
-  when (reg_time >= reg_mtimecmp) {
+  when (read_time >= reg_mtimecmp) {
     reg_mip.mtip := true
   }
 
@@ -409,7 +413,8 @@ class CSRFile extends CoreModule
     when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
     when (decoded_addr(CSRs.mcause))   { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
     when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
-    when (decoded_addr(CSRs.instretw)) { reg_instret := wdata }
+    if (params(UsePerfCounters))
+      when (decoded_addr(CSRs.instretw)) { reg_instret := wdata }
     when (decoded_addr(CSRs.mtimecmp)) { reg_mtimecmp := wdata; reg_mip.mtip := false }
     when (decoded_addr(CSRs.mtime))    { reg_time := wdata }
     when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index f8d9e862..ccc3950e 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -14,6 +14,7 @@ case object NMultXpr extends Field[Int]
 case object FetchWidth extends Field[Int]
 case object RetireWidth extends Field[Int]
 case object UseVM extends Field[Boolean]
+case object UsePerfCounters extends Field[Boolean]
 case object FastLoadWord extends Field[Boolean]
 case object FastLoadByte extends Field[Boolean]
 case object FastMulDiv extends Field[Boolean]

From 2f3d15675ce7b131fabcfebf6497bdc136a9e7d5 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Mon, 28 Sep 2015 16:02:29 -0700
Subject: [PATCH 24/35] fix DataArray writemask in L1D

---
 rocket/src/main/scala/nbdcache.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index d2fd5c1a..d1560cde 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -947,7 +947,7 @@ class HellaCache extends L1HellaCacheModule {
                              narrow_grant.bits.client_xact_id < UInt(nMSHRs)
   writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
   writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
-  writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
+  writeArb.io.in(1).bits.wmask := ~UInt(0, rowWords)
   writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
   data.io.read <> readArb.io.out
   readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked

From a7c908cb8303fac9801293e394a804da72ab5145 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 30 Sep 2015 12:43:00 -0700
Subject: [PATCH 25/35] Don't declare Reg inside of when

We haven't yet decided what the Chisel3 semantics for this will be.
---
 rocket/src/main/scala/btb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index b0ab7b11..d687c22e 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -174,6 +174,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
   }
 
   val updateHit = r_btb_update.bits.prediction.valid
+  val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
 
   val useUpdatePageHit = updatePageHit.orR
   val doIdxPageRepl = !useUpdatePageHit
@@ -196,7 +197,6 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
   when (r_btb_update.valid) {
     assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
 
-    val nextRepl = Counter(!updateHit, entries)._1
     val waddr =
       if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
       else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)

From 833909a2b544b4413a6c4bb6121b789cc61ba705 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 30 Sep 2015 14:36:26 -0700
Subject: [PATCH 26/35] Chisel3 compatibility fixes

---
 rocket/src/main/scala/btb.scala      | 18 +++++++++---------
 rocket/src/main/scala/fpu.scala      |  2 +-
 rocket/src/main/scala/nbdcache.scala |  2 +-
 rocket/src/main/scala/ptw.scala      |  4 ++--
 rocket/src/main/scala/rocket.scala   |  2 +-
 rocket/src/main/scala/tlb.scala      |  4 ++--
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index d687c22e..df6c433f 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -69,7 +69,7 @@ class BHT(nbht: Int) {
     when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
   }
 
-  private val table = Mem(UInt(width = 2), nbht)
+  private val table = Mem(nbht, UInt(width = 2))
   val history = Reg(UInt(width = nbhtbits))
 }
 
@@ -134,18 +134,18 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
   }
 
   val idxValid = Reg(init=UInt(0, entries))
-  val idxs = Mem(UInt(width=matchBits), entries)
-  val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
-  val tgts = Mem(UInt(width=matchBits), entries)
-  val tgtPages = Mem(UInt(width=log2Up(nPages)), entries)
-  val pages = Mem(UInt(width=vaddrBits-matchBits), nPages)
+  val idxs = Mem(entries, UInt(width=matchBits))
+  val idxPages = Mem(entries, UInt(width=log2Up(nPages)))
+  val tgts = Mem(entries, UInt(width=matchBits))
+  val tgtPages = Mem(entries, UInt(width=log2Up(nPages)))
+  val pages = Mem(nPages, UInt(width=vaddrBits-matchBits))
   val pageValid = Reg(init=UInt(0, nPages))
   val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
   val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
 
-  val useRAS = Reg(Vec(Bool(), entries))
-  val isJump = Reg(Vec(Bool(), entries))
-  val brIdx  = Mem(UInt(width=log2Up(params(FetchWidth))), entries)
+  val useRAS = Reg(Vec(entries, Bool()))
+  val isJump = Reg(Vec(entries, Bool()))
+  val brIdx  = Mem(entries, UInt(width=log2Up(params(FetchWidth))))
 
   private def page(addr: UInt) = addr >> matchBits
   private def pageMatch(addr: UInt) = {
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 10d657a2..daecb199 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -382,7 +382,7 @@ class FPU extends CoreModule
   val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d)
 
   // regfile
-  val regfile = Mem(Bits(width = 65), 32)
+  val regfile = Mem(32, Bits(width = 65))
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
     if (EnableCommitLog) {
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index d1560cde..bfbcdb11 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -387,7 +387,7 @@ class MSHRFile extends L1HellaCacheModule {
   val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
   val sdq_rdy = !sdq_val.andR
   val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
-  val sdq = Mem(io.req.bits.data, sdqDepth)
+  val sdq = Mem(sdqDepth, io.req.bits.data)
   when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
 
   val idxMatch = Wire(Vec(Bool(), nMSHRs))
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 1a49cee0..084eee2f 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -87,8 +87,8 @@ class PTW(n: Int) extends CoreModule
     val plru = new PseudoLRU(size)
     val valid = Reg(Vec(Bool(), size))
     val validBits = valid.toBits
-    val tags = Mem(UInt(width = paddrBits), size)
-    val data = Mem(UInt(width = ppnBits), size)
+    val tags = Mem(size, UInt(width = paddrBits))
+    val data = Mem(size, UInt(width = ppnBits))
 
     val hits = Vec(tags.map(_ === pte_addr)).toBits & validBits
     val hit = hits.orR
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index ccc3950e..30e33d0e 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -571,7 +571,7 @@ class Rocket extends CoreModule
   }
 
   class RegFile {
-    private val rf = Mem(UInt(width = 64), 31)
+    private val rf = Mem(31, UInt(width = 64))
     private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
     private var canRead = true
     def read(addr: UInt) = {
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index ce02f8ee..330c5989 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -33,7 +33,7 @@ class CAMIO extends TLBBundle {
 
 class RocketCAM extends TLBModule {
   val io = new CAMIO
-  val cam_tags = Mem(Bits(width = camTagBits), entries)
+  val cam_tags = Mem(entries, Bits(width = camTagBits))
 
   val vb_array = Reg(init=Bits(0, entries))
   when (io.write) {
@@ -109,7 +109,7 @@ class TLB extends TLBModule {
   val r_req = Reg(new TLBReq)
 
   val tag_cam = Module(new RocketCAM)
-  val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
+  val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
   
   val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
   tag_cam.io.tag := lookup_tag

From 19656e4abe3d3b776ae197027729d0f85855a28d Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 30 Sep 2015 16:58:10 -0700
Subject: [PATCH 27/35] make sure to generate release from clean coh state on
 probe miss

---
 rocket/src/main/scala/nbdcache.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index bfbcdb11..b06a8b89 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -630,7 +630,9 @@ class ProbeUnit extends L1HellaCacheModule {
     req := io.req.bits
   }
 
-  val reply = old_coh.makeRelease(req)
+  val miss_coh = ClientMetadata.onReset
+  val reply_coh = Mux(tag_matches, old_coh, miss_coh)
+  val reply = reply_coh.makeRelease(req)
   io.req.ready := state === s_invalid
   io.rep.valid := state === s_release &&
                   !(tag_matches && old_coh.requiresVoluntaryWriteback()) // Otherwise WBU will issue release

From 69a4dd0a798b0d1086e0a5c91a2f09a582a71538 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Fri, 2 Oct 2015 14:20:47 -0700
Subject: [PATCH 28/35] refactor NASTI to not use param

---
 rocket/src/main/scala/tlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 330c5989..478dd8f2 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -10,6 +10,7 @@ import scala.math._
 case object NTLBEntries extends Field[Int]
 
 abstract trait TLBParameters extends CoreParameters {
+  val addrMap = new AddrHashMap(params(NastiAddrMap))
   val entries = params(NTLBEntries)
   val camAddrBits = ceil(log(entries)/log(2)).toInt
   val camTagBits = asIdBits + vpnBits
@@ -167,7 +168,6 @@ class TLB extends TLBModule {
     plru.access(OHToUInt(tag_cam.io.hits))
   }
 
-  val addrMap = params(NASTIAddrHashMap)
   val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits))
   val addr_ok = addrMap.isValid(paddr)
   val addr_prot = addrMap.getProt(paddr)

From 84576650b57133b28bd4e2d3a57cb2d512dae5a5 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Mon, 5 Oct 2015 21:48:05 -0700
Subject: [PATCH 29/35] Removed all traces of params

---
 rocket/src/main/scala/arbiter.scala    |   2 +-
 rocket/src/main/scala/btb.scala        |  47 +++++----
 rocket/src/main/scala/csr.scala        |  98 +++++++++---------
 rocket/src/main/scala/dpath_alu.scala  |   5 +-
 rocket/src/main/scala/fpu.scala        |  13 ++-
 rocket/src/main/scala/frontend.scala   | 122 ++++++++++++++++++++++
 rocket/src/main/scala/icache.scala     | 135 ++-----------------------
 rocket/src/main/scala/multiplier.scala |  44 ++++----
 rocket/src/main/scala/nbdcache.scala   |  92 +++++++++--------
 rocket/src/main/scala/ptw.scala        |  13 ++-
 rocket/src/main/scala/rocc.scala       |  18 ++--
 rocket/src/main/scala/rocket.scala     | 102 ++++++++++---------
 rocket/src/main/scala/tile.scala       |  31 +++---
 rocket/src/main/scala/tlb.scala        |  26 ++---
 14 files changed, 383 insertions(+), 365 deletions(-)
 create mode 100644 rocket/src/main/scala/frontend.scala

diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index d995ff5f..14f20735 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 
-class HellaCacheArbiter(n: Int) extends Module
+class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
 {
   val io = new Bundle {
     val requestor = Vec(new HellaCacheIO, n).flip
diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index df6c433f..d0f51e6d 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -6,18 +6,23 @@ import Chisel._
 import junctions._
 import Util._
 
-case object NBTBEntries extends Field[Int]
-case object NRAS extends Field[Int]
+case object BtbKey extends Field[BtbParameters]
+case class BtbParameters(nEntries: Int = 62, nRAS: Int = 2, updatesOutOfOrder: Boolean = false)
 
-abstract trait BTBParameters extends CoreParameters {
-  val matchBits = params(PgIdxBits)
-  val entries = params(NBTBEntries)
-  val nRAS = params(NRAS)
+abstract trait HasBtbParameters extends HasCoreParameters {
+  val matchBits = p(PgIdxBits)
+  val entries = p(BtbKey).nEntries
+  val nRAS = p(BtbKey).nRAS
+  val updatesOutOfOrder = p(BtbKey).updatesOutOfOrder
   val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
   val opaqueBits = log2Up(entries)
   val nBHT = 1 << log2Up(entries*2)
 }
 
+abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
+abstract class BtbBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
+  with HasBtbParameters
+
 class RAS(nras: Int) {
   def push(addr: UInt): Unit = {
     when (count < nras) { count := count + 1 }
@@ -38,7 +43,7 @@ class RAS(nras: Int) {
   private val stack = Reg(Vec(UInt(), nras))
 }
 
-class BHTResp extends Bundle with BTBParameters {
+class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
   val history = UInt(width = log2Up(nBHT).max(1))
   val value = UInt(width = 2)
 }
@@ -52,7 +57,7 @@ class BHTResp extends Bundle with BTBParameters {
 //    - each counter corresponds with the address of the fetch packet ("fetch pc").
 //    - updated when a branch resolves (and BTB was a hit for that branch).
 //      The updating branch must provide its "fetch pc".
-class BHT(nbht: Int) {
+class BHT(nbht: Int)(implicit p: Parameters) {
   val nbhtbits = log2Up(nbht)
   def get(addr: UInt, update: Bool): BHTResp = {
     val res = Wire(new BHTResp)
@@ -76,7 +81,7 @@ class BHT(nbht: Int) {
 // BTB update occurs during branch resolution (and only on a mispredict).
 //  - "pc" is what future fetch PCs will tag match against.
 //  - "br_pc" is the PC of the branch instruction.
-class BTBUpdate extends Bundle with BTBParameters {
+class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
   val prediction = Valid(new BTBResp)
   val pc = UInt(width = vaddrBits)
   val target = UInt(width = vaddrBits)
@@ -88,14 +93,14 @@ class BTBUpdate extends Bundle with BTBParameters {
 
 // BHT update occurs during branch resolution on all conditional branches.
 //  - "pc" is what future fetch PCs will tag match against.
-class BHTUpdate extends Bundle with BTBParameters {
+class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
   val prediction = Valid(new BTBResp)
   val pc = UInt(width = vaddrBits)
   val taken = Bool()
   val mispredict = Bool()
 }
 
-class RASUpdate extends Bundle with BTBParameters {
+class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
   val isCall = Bool()
   val isReturn = Bool()
   val returnAddr = UInt(width = vaddrBits)
@@ -106,16 +111,16 @@ class RASUpdate extends Bundle with BTBParameters {
 //     shifting off the lowest log(inst_bytes) bits off).
 //  - "resp.mask" provides a mask of valid instructions (instructions are
 //     masked off by the predicted taken branch).
-class BTBResp extends Bundle with BTBParameters {
+class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
   val taken = Bool()
-  val mask = Bits(width = params(FetchWidth))
-  val bridx = Bits(width = log2Up(params(FetchWidth)))
+  val mask = Bits(width = fetchWidth)
+  val bridx = Bits(width = log2Up(fetchWidth))
   val target = UInt(width = vaddrBits)
   val entry = UInt(width = opaqueBits)
   val bht = new BHTResp
 }
 
-class BTBReq extends Bundle with BTBParameters {
+class BTBReq(implicit p: Parameters) extends BtbBundle()(p) {
    val addr = UInt(width = vaddrBits)
 }
 
@@ -123,7 +128,7 @@ class BTBReq extends Bundle with BTBParameters {
 // Higher-performance processors may cause BTB updates to occur out-of-order,
 // which requires an extra CAM port for updates (to ensure no duplicates get
 // placed in BTB).
-class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParameters {
+class BTB(implicit p: Parameters) extends BtbModule {
   val io = new Bundle {
     val req = Valid(new BTBReq).flip
     val resp = Valid(new BTBResp)
@@ -145,7 +150,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
 
   val useRAS = Reg(Vec(entries, Bool()))
   val isJump = Reg(Vec(entries, Bool()))
-  val brIdx  = Mem(entries, UInt(width=log2Up(params(FetchWidth))))
+  val brIdx  = Mem(entries, UInt(width=log2Up(fetchWidth)))
 
   private def page(addr: UInt) = addr >> matchBits
   private def pageMatch(addr: UInt) = {
@@ -198,7 +203,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
     assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
 
     val waddr =
-      if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
+      if (updatesOutOfOrder) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
       else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
 
     // invalidate entries if we stomp on pages they depend upon
@@ -212,10 +217,10 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
     tgtPages(waddr) := tgtPageUpdate
     useRAS(waddr) := r_btb_update.bits.isReturn
     isJump(waddr) := r_btb_update.bits.isJump
-    if (params(FetchWidth) == 1) {
+    if (fetchWidth == 1) {
       brIdx(waddr) := UInt(0)
     } else {
-      brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
+      brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes)
     }
 
     require(nPages % 2 == 0)
@@ -243,7 +248,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
   io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
   io.resp.bits.entry := OHToUInt(hits)
   io.resp.bits.bridx := brIdx(io.resp.bits.entry)
-  if (params(FetchWidth) == 1) {
+  if (fetchWidth == 1) {
     io.resp.bits.mask := UInt(1)
   } else {
     // note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 6b7f6b79..cb9bb685 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -64,12 +64,14 @@ object CSR
   val C = UInt(3,SZ)
   val I = UInt(4,SZ)
   val R = UInt(5,SZ)
+
+  val ADDRSZ = 12
 }
 
-class CSRFileIO extends CoreBundle {
-  val host = new HTIFIO
+class CSRFileIO(implicit p: Parameters) extends CoreBundle {
+  val host = new HtifIO
   val rw = new Bundle {
-    val addr = UInt(INPUT, 12)
+    val addr = UInt(INPUT, CSR.ADDRSZ)
     val cmd = Bits(INPUT, CSR.SZ)
     val rdata = Bits(OUTPUT, xLen)
     val wdata = Bits(INPUT, xLen)
@@ -86,7 +88,7 @@ class CSRFileIO extends CoreBundle {
   val exception = Bool(INPUT)
   val retire = UInt(INPUT, log2Up(1+retireWidth))
   val uarch_counters = Vec(UInt(INPUT, log2Up(1+retireWidth)), 16)
-  val custom_mrw_csrs = Vec(UInt(INPUT, xLen), params(NCustomMRWCSRs))
+  val custom_mrw_csrs = Vec(UInt(INPUT, xLen), nCustomMrwCsrs)
   val cause = UInt(INPUT, xLen)
   val pc = UInt(INPUT, vaddrBitsExtended)
   val fatc = Bool(OUTPUT)
@@ -98,7 +100,7 @@ class CSRFileIO extends CoreBundle {
   val interrupt_cause = UInt(OUTPUT, xLen)
 }
 
-class CSRFile extends CoreModule
+class CSRFile(implicit p: Parameters) extends CoreModule()(p)
 {
   val io = new CSRFileIO
 
@@ -124,12 +126,12 @@ class CSRFile extends CoreModule
   val reg_stats = Reg(init=Bool(false))
   val reg_time = Reg(UInt(width = xLen))
   val reg_instret = WideCounter(xLen, io.retire)
-  val reg_cycle = if (EnableCommitLog) { reg_instret } else { WideCounter(xLen) }
+  val reg_cycle = if (enableCommitLog) { reg_instret } else { WideCounter(xLen) }
   val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))
 
-  val irq_rocc = Bool(!params(BuildRoCC).isEmpty) && io.rocc.interrupt
+  val irq_rocc = Bool(!p(BuildRoCC).isEmpty) && io.rocc.interrupt
 
   io.interrupt_cause := 0
   io.interrupt := io.interrupt_cause(xLen-1)
@@ -153,40 +155,40 @@ class CSRFile extends CoreModule
   val system_insn = io.rw.cmd === CSR.I
   val cpu_ren = io.rw.cmd != CSR.N && !system_insn
 
-  val host_pcr_req_valid = Reg(Bool()) // don't reset
-  val host_pcr_req_fire = host_pcr_req_valid && !cpu_ren
-  val host_pcr_rep_valid = Reg(Bool()) // don't reset
-  val host_pcr_bits = Reg(io.host.pcr.req.bits)
-  io.host.pcr.req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
-  io.host.pcr.resp.valid := host_pcr_rep_valid
-  io.host.pcr.resp.bits := host_pcr_bits.data
-  when (io.host.pcr.req.fire()) {
-    host_pcr_req_valid := true
-    host_pcr_bits := io.host.pcr.req.bits
+  val host_csr_req_valid = Reg(Bool()) // don't reset
+  val host_csr_req_fire = host_csr_req_valid && !cpu_ren
+  val host_csr_rep_valid = Reg(Bool()) // don't reset
+  val host_csr_bits = Reg(io.host.csr.req.bits)
+  io.host.csr.req.ready := !host_csr_req_valid && !host_csr_rep_valid
+  io.host.csr.resp.valid := host_csr_rep_valid
+  io.host.csr.resp.bits := host_csr_bits.data
+  when (io.host.csr.req.fire()) {
+    host_csr_req_valid := true
+    host_csr_bits := io.host.csr.req.bits
   }
-  when (host_pcr_req_fire) {
-    host_pcr_req_valid := false
-    host_pcr_rep_valid := true
-    host_pcr_bits.data := io.rw.rdata
+  when (host_csr_req_fire) {
+    host_csr_req_valid := false
+    host_csr_rep_valid := true
+    host_csr_bits.data := io.rw.rdata
   }
-  when (io.host.pcr.resp.fire()) { host_pcr_rep_valid := false }
+  when (io.host.csr.resp.fire()) { host_csr_rep_valid := false }
 
-  io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
+  io.host.debug_stats_csr := reg_stats // direct export up the hierarchy
 
-  val read_time = if (params(UsePerfCounters)) reg_time else (reg_cycle: UInt)
+  val read_time = if (usingPerfCounters) reg_time else (reg_cycle: UInt)
   val read_mstatus = io.status.toBits
   val isa_string = "IMA" +
-    (if (params(UseVM)) "S" else "") +
-    (if (!params(BuildFPU).isEmpty) "FD" else "") +
-    (if (!params(BuildRoCC).isEmpty) "X" else "")
+    (if (usingVM) "S" else "") +
+    (if (usingFPU) "FD" else "") +
+    (if (usingRoCC) "X" else "")
   val cpuid = ((if (xLen == 32) BigInt(0) else BigInt(2)) << (xLen-2)) |
     isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
   val impid = 1
 
   val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
-    CSRs.fflags -> (if (!params(BuildFPU).isEmpty) reg_fflags else UInt(0)),
-    CSRs.frm -> (if (!params(BuildFPU).isEmpty) reg_frm else UInt(0)),
-    CSRs.fcsr -> (if (!params(BuildFPU).isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
+    CSRs.fflags -> (if (usingFPU) reg_fflags else UInt(0)),
+    CSRs.frm -> (if (usingFPU) reg_frm else UInt(0)),
+    CSRs.fcsr -> (if (usingFPU) Cat(reg_frm, reg_fflags) else UInt(0)),
     CSRs.cycle -> reg_cycle,
     CSRs.cyclew -> reg_cycle,
     CSRs.time -> read_time,
@@ -213,7 +215,7 @@ class CSRFile extends CoreModule
     CSRs.mtohost -> reg_tohost,
     CSRs.mfromhost -> reg_fromhost)
 
-  if (params(UsePerfCounters)) {
+  if (usingPerfCounters) {
     read_mapping += CSRs.instret -> reg_instret
     read_mapping += CSRs.instretw -> reg_instret
 
@@ -221,7 +223,7 @@ class CSRFile extends CoreModule
       read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
   }
 
-  if (params(UseVM)) {
+  if (usingVM) {
     val read_sstatus = Wire(init=new SStatus().fromBits(read_mstatus))
     read_sstatus.zero1 := 0
     read_sstatus.zero2 := 0
@@ -248,14 +250,14 @@ class CSRFile extends CoreModule
     read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
   }
 
-  for (i <- 0 until params(NCustomMRWCSRs)) {
+  for (i <- 0 until nCustomMrwCsrs) {
     val addr = 0x790 + i // turn 0x790 into parameter CustomMRWCSRBase?
     require(addr >= 0x780 && addr <= 0x7ff, "custom MRW CSR address " + i + " is out of range")
     require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
     read_mapping += addr -> io.custom_mrw_csrs(i)
   }
 
-  val addr = Mux(cpu_ren, io.rw.addr, host_pcr_bits.addr)
+  val addr = Mux(cpu_ren, io.rw.addr, host_csr_bits.addr)
   val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) }
 
   val addr_valid = decoded_addr.values.reduce(_||_)
@@ -264,11 +266,11 @@ class CSRFile extends CoreModule
   val priv_sufficient = reg_mstatus.prv >= csr_addr_priv
   val read_only = io.rw.addr(11,10).andR
   val cpu_wen = cpu_ren && io.rw.cmd != CSR.R && priv_sufficient
-  val wen = cpu_wen && !read_only || host_pcr_req_fire && host_pcr_bits.rw
+  val wen = cpu_wen && !read_only || host_csr_req_fire && host_csr_bits.rw
   val wdata = Mux(io.rw.cmd === CSR.W, io.rw.wdata,
               Mux(io.rw.cmd === CSR.C, io.rw.rdata & ~io.rw.wdata,
               Mux(io.rw.cmd === CSR.S, io.rw.rdata | io.rw.wdata,
-              host_pcr_bits.data)))
+              host_csr_bits.data)))
 
   val opcode = io.rw.addr
   val insn_call = !opcode(8) && !opcode(0) && system_insn
@@ -355,7 +357,7 @@ class CSRFile extends CoreModule
   io.csr_replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
   io.csr_stall := reg_wfi
 
-  when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
+  when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
 
   io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
 
@@ -370,7 +372,7 @@ class CSRFile extends CoreModule
       reg_mstatus.ie := new_mstatus.ie
       reg_mstatus.ie1 := new_mstatus.ie1
 
-      val supportedModes = Vec((PRV_M :: PRV_U :: (if (params(UseVM)) List(PRV_S) else Nil)).map(UInt(_)))
+      val supportedModes = Vec((PRV_M :: PRV_U :: (if (usingVM) List(PRV_S) else Nil)).map(UInt(_)))
       if (supportedModes.size > 1) {
         reg_mstatus.mprv := new_mstatus.mprv
         when (supportedModes contains new_mstatus.prv) { reg_mstatus.prv := new_mstatus.prv }
@@ -381,17 +383,17 @@ class CSRFile extends CoreModule
         }
       }
 
-      if (params(UseVM)) {
+      if (usingVM) {
         val vm_on = if (xLen == 32) 8 else 9
         when (new_mstatus.vm === 0) { reg_mstatus.vm := 0 }
         when (new_mstatus.vm === vm_on) { reg_mstatus.vm := vm_on }
       }
-      if (params(UseVM) || !params(BuildFPU).isEmpty) reg_mstatus.fs := new_mstatus.fs
-      if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_mstatus.xs
+      if (usingVM || usingFPU) reg_mstatus.fs := new_mstatus.fs
+      if (usingRoCC) reg_mstatus.xs := new_mstatus.xs
     }
     when (decoded_addr(CSRs.mip)) {
       val new_mip = new MIP().fromBits(wdata)
-      if (params(UseVM)) {
+      if (usingVM) {
         reg_mip.ssip := new_mip.ssip
         reg_mip.stip := new_mip.stip
       }
@@ -399,7 +401,7 @@ class CSRFile extends CoreModule
     }
     when (decoded_addr(CSRs.mie)) {
       val new_mie = new MIP().fromBits(wdata)
-      if (params(UseVM)) {
+      if (usingVM) {
         reg_mie.ssip := new_mie.ssip
         reg_mie.stip := new_mie.stip
       }
@@ -413,14 +415,14 @@ class CSRFile extends CoreModule
     when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
     when (decoded_addr(CSRs.mcause))   { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
     when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
-    if (params(UsePerfCounters))
+    if (usingPerfCounters)
       when (decoded_addr(CSRs.instretw)) { reg_instret := wdata }
     when (decoded_addr(CSRs.mtimecmp)) { reg_mtimecmp := wdata; reg_mip.mtip := false }
     when (decoded_addr(CSRs.mtime))    { reg_time := wdata }
-    when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
-    when (decoded_addr(CSRs.mtohost))  { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
+    when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_csr_req_fire) { reg_fromhost := wdata } }
+    when (decoded_addr(CSRs.mtohost))  { when (reg_tohost === UInt(0) || host_csr_req_fire) { reg_tohost := wdata } }
     when (decoded_addr(CSRs.stats))    { reg_stats := wdata(0) }
-    if (params(UseVM)) {
+    if (usingVM) {
       when (decoded_addr(CSRs.sstatus)) {
         val new_sstatus = new SStatus().fromBits(wdata)
         reg_mstatus.ie := new_sstatus.ie
@@ -428,7 +430,7 @@ class CSRFile extends CoreModule
         reg_mstatus.prv1 := Mux[UInt](new_sstatus.ps, PRV_S, PRV_U)
         reg_mstatus.mprv := new_sstatus.mprv
         reg_mstatus.fs := new_sstatus.fs // even without an FPU
-        if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs
+        if (usingRoCC) reg_mstatus.xs := new_sstatus.xs
       }
       when (decoded_addr(CSRs.sip)) {
         val new_sip = new MIP().fromBits(wdata)
diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala
index 354934ca..5142c611 100644
--- a/rocket/src/main/scala/dpath_alu.scala
+++ b/rocket/src/main/scala/dpath_alu.scala
@@ -42,7 +42,7 @@ object ALU
 }
 import ALU._
 
-class ALUIO extends CoreBundle {
+class ALUIO(implicit p: Parameters) extends CoreBundle()(p) {
   val dw = Bits(INPUT, SZ_DW)
   val fn = Bits(INPUT, SZ_ALU_FN)
   val in2 = UInt(INPUT, xLen)
@@ -51,8 +51,7 @@ class ALUIO extends CoreBundle {
   val adder_out = UInt(OUTPUT, xLen)
 }
 
-class ALU extends Module
-{
+class ALU(implicit p: Parameters) extends Module {
   val io = new ALUIO
 
   // ADD, SUB
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index daecb199..c456413c 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -353,8 +353,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
   io.out := Pipe(valid, res, latency-1)
 }
 
-class FPU extends CoreModule
-{
+class FPU(implicit p: Parameters) extends CoreModule()(p) {
   val io = new FPUIO
 
   val ex_reg_valid = Reg(next=io.valid, init=Bool(false))
@@ -385,7 +384,7 @@ class FPU extends CoreModule
   val regfile = Mem(32, Bits(width = 65))
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
-    if (EnableCommitLog) {
+    if (enableCommitLog) {
       printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32),
         Mux(load_wb_single, load_wb_data(31,0), load_wb_data))
     }
@@ -415,11 +414,11 @@ class FPU extends CoreModule
   req.in3 := ex_rs3
   req.typ := ex_reg_inst(21,20)
 
-  val sfma = Module(new FPUFMAPipe(params(SFMALatency), 23, 9))
+  val sfma = Module(new FPUFMAPipe(p(SFMALatency), 23, 9))
   sfma.io.in.valid := ex_reg_valid && ex_ctrl.fma && ex_ctrl.single
   sfma.io.in.bits := req
 
-  val dfma = Module(new FPUFMAPipe(params(DFMALatency), 52, 12))
+  val dfma = Module(new FPUFMAPipe(p(DFMALatency), 52, 12))
   dfma.io.in.valid := ex_reg_valid && ex_ctrl.fma && !ex_ctrl.single
   dfma.io.in.bits := req
 
@@ -488,7 +487,7 @@ class FPU extends CoreModule
   val wexc = Vec(pipes.map(_.res.exc))(wsrc)
   when (wen(0) || divSqrt_wen) {
     regfile(waddr) := wdata 
-    if (EnableCommitLog) {
+    if (enableCommitLog) {
       val wdata_unrec_s = hardfloat.recodedFloatNToFloatN(wdata(64,0), 23, 9)
       val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
       val wb_single = (winfo(0) >> 5)(0)
@@ -518,7 +517,7 @@ class FPU extends CoreModule
 
   divSqrt_wdata := 0
   divSqrt_flags := 0
-  if (params(FDivSqrt)) {
+  if (p(FDivSqrt)) {
     val divSqrt_single = Reg(Bool())
     val divSqrt_rm = Reg(Bits())
     val divSqrt_flags_double = Reg(Bits())
diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
new file mode 100644
index 00000000..15fb6266
--- /dev/null
+++ b/rocket/src/main/scala/frontend.scala
@@ -0,0 +1,122 @@
+package rocket
+
+import Chisel._
+import uncore._
+import Util._
+
+class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
+  val pc = UInt(width = vaddrBitsExtended)
+}
+
+class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
+  val pc = UInt(width = vaddrBitsExtended)  // ID stage PC
+  val data = Vec(Bits(width = coreInstBits), fetchWidth)
+  val mask = Bits(width = fetchWidth)
+  val xcpt_if = Bool()
+}
+
+class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
+  val req = Valid(new FrontendReq)
+  val resp = Decoupled(new FrontendResp).flip
+  val btb_resp = Valid(new BTBResp).flip
+  val btb_update = Valid(new BTBUpdate)
+  val bht_update = Valid(new BHTUpdate)
+  val ras_update = Valid(new RASUpdate)
+  val invalidate = Bool(OUTPUT)
+  val npc = UInt(INPUT, width = vaddrBitsExtended)
+}
+
+class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
+  val io = new Bundle {
+    val cpu = new FrontendIO().flip
+    val ptw = new TLBPTWIO()
+    val mem = new ClientUncachedTileLinkIO
+  }
+
+  val btb = Module(new BTB)
+  val icache = Module(new ICache)
+  val tlb = Module(new TLB)
+
+  val s1_pc_ = Reg(UInt())
+  val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
+  val s1_same_block = Reg(Bool())
+  val s2_valid = Reg(init=Bool(true))
+  val s2_pc = Reg(init=UInt(START_ADDR))
+  val s2_btb_resp_valid = Reg(init=Bool(false))
+  val s2_btb_resp_bits = Reg(btb.io.resp.bits)
+  val s2_xcpt_if = Reg(init=Bool(false))
+
+  val msb = vaddrBits-1
+  val lsb = log2Up(fetchWidth*coreInstBytes)
+  val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
+  val ntpc_0 = s1_pc + UInt(coreInstBytes*fetchWidth)
+  val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
+  val icmiss = s2_valid && !icache.io.resp.valid
+  val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
+  val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
+  val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
+
+  val stall = io.cpu.resp.valid && !io.cpu.resp.ready
+  when (!stall) {
+    s1_same_block := s0_same_block && !tlb.io.resp.miss
+    s1_pc_ := npc
+    s2_valid := !icmiss
+    when (!icmiss) {
+      s2_pc := s1_pc
+      s2_btb_resp_valid := btb.io.resp.valid
+      when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
+      s2_xcpt_if := tlb.io.resp.xcpt_if
+    }
+  }
+  when (io.cpu.req.valid) {
+    s1_same_block := Bool(false)
+    s1_pc_ := io.cpu.req.bits.pc
+    s2_valid := Bool(false)
+  }
+
+  btb.io.req.valid := !stall && !icmiss
+  btb.io.req.bits.addr := s1_pc
+  btb.io.btb_update := io.cpu.btb_update
+  btb.io.bht_update := io.cpu.bht_update
+  btb.io.ras_update := io.cpu.ras_update
+  btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
+
+  io.ptw <> tlb.io.ptw
+  tlb.io.req.valid := !stall && !icmiss
+  tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
+  tlb.io.req.bits.asid := UInt(0)
+  tlb.io.req.bits.passthrough := Bool(false)
+  tlb.io.req.bits.instruction := Bool(true)
+  tlb.io.req.bits.store := Bool(false)
+
+  io.mem <> icache.io.mem
+  icache.io.req.valid := !stall && !s0_same_block
+  icache.io.req.bits.idx := io.cpu.npc
+  icache.io.invalidate := io.cpu.invalidate
+  icache.io.req.bits.ppn := tlb.io.resp.ppn
+  icache.io.req.bits.kill := io.cpu.req.valid ||
+    tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
+    icmiss || io.ptw.invalidate
+  icache.io.resp.ready := !stall && !s1_same_block
+
+  io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
+  io.cpu.resp.bits.pc := s2_pc
+  io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
+
+  require(fetchWidth * coreInstBytes <= rowBytes)
+  val fetch_data =
+    if (fetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
+    else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(fetchWidth*coreInstBytes)) << log2Up(fetchWidth*coreInstBits))
+
+  for (i <- 0 until fetchWidth) {
+    io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
+  }
+
+  val all_ones = UInt((1 << (fetchWidth+1))-1)
+  val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
+  io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
+  io.cpu.resp.bits.xcpt_if := s2_xcpt_if
+
+  io.cpu.btb_resp.valid := s2_btb_resp_valid
+  io.cpu.btb_resp.bits := s2_btb_resp_bits
+}
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index f9650b95..b7f2c565 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -4,148 +4,25 @@ import Chisel._
 import uncore._
 import Util._
 
-abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
-  val outerDataBeats = params(TLDataBeats)
-  val outerDataBits = params(TLDataBits)
+trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
+  val outerDataBeats = p(TLDataBeats)
+  val outerDataBits = p(TLDataBits)
   val refillCyclesPerBeat = outerDataBits/rowBits
   val refillCycles = refillCyclesPerBeat*outerDataBeats
 }
 
-abstract trait FrontendParameters extends L1CacheParameters
-abstract class FrontendBundle extends Bundle with FrontendParameters
-abstract class FrontendModule extends Module with FrontendParameters
-
-class FrontendReq extends CoreBundle {
-  val pc = UInt(width = vaddrBitsExtended)
-}
-
-class FrontendResp extends CoreBundle {
-  val pc = UInt(width = vaddrBitsExtended)  // ID stage PC
-  val data = Vec(Bits(width = coreInstBits), coreFetchWidth)
-  val mask = Bits(width = coreFetchWidth)
-  val xcpt_if = Bool()
-}
-
-class CPUFrontendIO extends CoreBundle {
-  val req = Valid(new FrontendReq)
-  val resp = Decoupled(new FrontendResp).flip
-  val btb_resp = Valid(new BTBResp).flip
-  val btb_update = Valid(new BTBUpdate)
-  val bht_update = Valid(new BHTUpdate)
-  val ras_update = Valid(new RASUpdate)
-  val invalidate = Bool(OUTPUT)
-  val npc = UInt(INPUT, width = vaddrBitsExtended)
-}
-
-class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
-{
-  val io = new Bundle {
-    val cpu = new CPUFrontendIO().flip
-    val ptw = new TLBPTWIO()
-    val mem = new ClientUncachedTileLinkIO
-  }
-
-  val btb = Module(new BTB(btb_updates_out_of_order))
-  val icache = Module(new ICache)
-  val tlb = Module(new TLB)
-
-  val s1_pc_ = Reg(UInt())
-  val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
-  val s1_same_block = Reg(Bool())
-  val s2_valid = Reg(init=Bool(true))
-  val s2_pc = Reg(init=UInt(START_ADDR))
-  val s2_btb_resp_valid = Reg(init=Bool(false))
-  val s2_btb_resp_bits = Reg(btb.io.resp.bits)
-  val s2_xcpt_if = Reg(init=Bool(false))
-
-  val msb = vaddrBits-1
-  val lsb = log2Up(coreFetchWidth*coreInstBytes)
-  val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
-  val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
-  val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
-  val icmiss = s2_valid && !icache.io.resp.valid
-  val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
-  val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
-  val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
-
-  val stall = io.cpu.resp.valid && !io.cpu.resp.ready
-  when (!stall) {
-    s1_same_block := s0_same_block && !tlb.io.resp.miss
-    s1_pc_ := npc
-    s2_valid := !icmiss
-    when (!icmiss) {
-      s2_pc := s1_pc
-      s2_btb_resp_valid := btb.io.resp.valid
-      when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
-      s2_xcpt_if := tlb.io.resp.xcpt_if
-    }
-  }
-  when (io.cpu.req.valid) {
-    s1_same_block := Bool(false)
-    s1_pc_ := io.cpu.req.bits.pc
-    s2_valid := Bool(false)
-  }
-
-  btb.io.req.valid := !stall && !icmiss
-  btb.io.req.bits.addr := s1_pc
-  btb.io.btb_update := io.cpu.btb_update
-  btb.io.bht_update := io.cpu.bht_update
-  btb.io.ras_update := io.cpu.ras_update
-  btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
-
-  io.ptw <> tlb.io.ptw
-  tlb.io.req.valid := !stall && !icmiss
-  tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
-  tlb.io.req.bits.asid := UInt(0)
-  tlb.io.req.bits.passthrough := Bool(false)
-  tlb.io.req.bits.instruction := Bool(true)
-  tlb.io.req.bits.store := Bool(false)
-
-  io.mem <> icache.io.mem
-  icache.io.req.valid := !stall && !s0_same_block
-  icache.io.req.bits.idx := io.cpu.npc
-  icache.io.invalidate := io.cpu.invalidate
-  icache.io.req.bits.ppn := tlb.io.resp.ppn
-  icache.io.req.bits.kill := io.cpu.req.valid ||
-    tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
-    icmiss || io.ptw.invalidate
-  icache.io.resp.ready := !stall && !s1_same_block
-
-  io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
-  io.cpu.resp.bits.pc := s2_pc
-  io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
-
-  require(coreFetchWidth * coreInstBytes <= rowBytes)
-  val fetch_data =
-    if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
-    else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
-
-  for (i <- 0 until coreFetchWidth) {
-    io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
-  }
-
-  val all_ones = UInt((1 << (coreFetchWidth+1))-1)
-  val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
-  io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
-  io.cpu.resp.bits.xcpt_if := s2_xcpt_if
-
-  io.cpu.btb_resp.valid := s2_btb_resp_valid
-  io.cpu.btb_resp.bits := s2_btb_resp_bits
-}
-
-class ICacheReq extends FrontendBundle {
+class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) {
   val idx = UInt(width = pgIdxBits)
   val ppn = UInt(width = ppnBits) // delayed one cycle
   val kill = Bool() // delayed one cycle
 }
 
-class ICacheResp extends FrontendBundle {
+class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
   val data = Bits(width = coreInstBits)
   val datablock = Bits(width = rowBits)
 }
 
-class ICache extends FrontendModule
-{
+class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
   val io = new Bundle {
     val req = Valid(new ICacheReq).flip
     val resp = Decoupled(new ICacheResp)
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index 6498aa2d..f6f4c9be 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -6,29 +6,35 @@ import Chisel._
 import ALU._
 import Util._
 
-class MultiplierReq extends CoreBundle {
+class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
   val fn = Bits(width = SZ_ALU_FN)
   val dw = Bits(width = SZ_DW)
-  val in1 = Bits(width = xLen)
-  val in2 = Bits(width = xLen)
-  val tag = UInt(width = log2Up(params(NMultXpr)))
+  val in1 = Bits(width = dataBits)
+  val in2 = Bits(width = dataBits)
+  val tag = UInt(width = tagBits)
+  override def cloneType = new MultiplierReq(dataBits, tagBits).asInstanceOf[this.type]
 }
 
-class MultiplierResp extends CoreBundle {
-  val data = Bits(width = xLen)
-  val tag = UInt(width = log2Up(params(NMultXpr)))
+class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
+  val data = Bits(width = dataBits)
+  val tag = UInt(width = tagBits)
+  override def cloneType = new MultiplierResp(dataBits, tagBits).asInstanceOf[this.type]
 }
 
-class MultiplierIO extends Bundle {
-  val req = Decoupled(new MultiplierReq).flip
+class MultiplierIO(dataBits: Int, tagBits: Int) extends Bundle {
+  val req = Decoupled(new MultiplierReq(dataBits, tagBits)).flip
   val kill = Bool(INPUT)
-  val resp = Decoupled(new MultiplierResp)
+  val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
 }
 
-class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false) extends Module {
-  val io = new MultiplierIO
+class MulDiv(
+    width: Int,
+    nXpr: Int = 32,
+    unroll: Int = 1,
+    earlyOut: Boolean = false) extends Module {
+  val io = new MultiplierIO(width, log2Up(nXpr))
   val w = io.req.bits.in1.getWidth
-  val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
+  val mulw = (w+unroll-1)/unroll*unroll
  
   val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
   val state = Reg(init=s_ready)
@@ -87,18 +93,18 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false) extends Module {
     val mplier = mulReg(mulw-1,0)
     val accum = mulReg(2*mulw,mulw).toSInt
     val mpcand = divisor.toSInt
-    val prod = mplier(mulUnroll-1,0) * mpcand + accum
-    val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
+    val prod = mplier(unroll-1,0) * mpcand + accum
+    val nextMulReg = Cat(prod, mplier(mulw-1,unroll)).toUInt
 
-    val eOutMask = (SInt(BigInt(-1) << mulw) >> (count * mulUnroll)(log2Up(mulw)-1,0))(mulw-1,0)
-    val eOut = Bool(earlyOut) && count != mulw/mulUnroll-1 && count != 0 &&
+    val eOutMask = (SInt(BigInt(-1) << mulw) >> (count * unroll)(log2Up(mulw)-1,0))(mulw-1,0)
+    val eOut = Bool(earlyOut) && count != mulw/unroll-1 && count != 0 &&
       !isHi && (mplier & ~eOutMask) === UInt(0)
-    val eOutRes = (mulReg >> (mulw - count * mulUnroll)(log2Up(mulw)-1,0))
+    val eOutRes = (mulReg >> (mulw - count * unroll)(log2Up(mulw)-1,0))
     val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
     remainder := Cat(nextMulReg1 >> w, Bool(false), nextMulReg1(w-1,0))
 
     count := count + 1
-    when (eOut || count === mulw/mulUnroll-1) {
+    when (eOut || count === mulw/unroll-1) {
       state := Mux(isHi, s_move_rem, s_done)
     }
   }
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index b06a8b89..d71cbf8f 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -14,11 +14,11 @@ case object NMSHRs extends Field[Int]
 case object NIOMSHRs extends Field[Int]
 case object LRSCCycles extends Field[Int]
 
-abstract trait L1HellaCacheParameters extends L1CacheParameters {
-  val wordBits = params(WordBits)
+trait HasL1HellaCacheParameters extends HasL1CacheParameters {
+  val wordBits = p(WordBits)
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
-  val beatBytes = params(CacheBlockBytes) / params(TLDataBeats)
+  val beatBytes = p(CacheBlockBytes) / p(TLDataBeats)
   val beatWords = beatBytes / wordBytes
   val beatOffBits = log2Up(beatBytes)
   val idxMSB = untagBits-1
@@ -29,43 +29,48 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
   val doNarrowRead = coreDataBits * nWays % rowBits == 0
   val encDataBits = code.width(coreDataBits)
   val encRowBits = encDataBits*rowWords
-  val sdqDepth = params(StoreDataQueueDepth)
-  val nMSHRs = params(NMSHRs)
-  val nIOMSHRs = params(NIOMSHRs)
+  val sdqDepth = p(StoreDataQueueDepth)
+  val nMSHRs = p(NMSHRs)
+  val nIOMSHRs = p(NIOMSHRs)
 }
 
-abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
-abstract class L1HellaCacheModule extends Module with L1HellaCacheParameters
+abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
+  with HasL1HellaCacheParameters
+abstract class L1HellaCacheBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
+  with HasL1HellaCacheParameters
 
-trait HasCoreMemOp extends CoreBundle {
+trait HasCoreMemOp extends HasCoreParameters {
   val addr = UInt(width = coreMaxAddrBits)
   val tag  = Bits(width = coreDCacheReqTagBits)
   val cmd  = Bits(width = M_SZ)
   val typ  = Bits(width = MT_SZ)
 }
 
-trait HasCoreData extends CoreBundle {
+trait HasCoreData extends HasCoreParameters {
   val data = Bits(width = coreDataBits)
 }
 
-trait HasSDQId extends CoreBundle with L1HellaCacheParameters {
+trait HasSDQId extends HasL1HellaCacheParameters {
   val sdq_id = UInt(width = log2Up(sdqDepth))
 }
 
-trait HasMissInfo extends CoreBundle with L1HellaCacheParameters {
+trait HasMissInfo extends HasL1HellaCacheParameters {
   val tag_match = Bool()
   val old_meta = new L1Metadata
   val way_en = Bits(width = nWays)
 }
 
-class HellaCacheReqInternal extends HasCoreMemOp {
+class HellaCacheReqInternal(implicit p: Parameters) extends L1HellaCacheBundle()(p)
+    with HasCoreMemOp {
   val kill = Bool()
   val phys = Bool()
 }
 
-class HellaCacheReq extends HellaCacheReqInternal with HasCoreData
+class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
 
-class HellaCacheResp extends HasCoreMemOp with HasCoreData {
+class HellaCacheResp(implicit p: Parameters) extends L1HellaCacheBundle()(p)
+    with HasCoreMemOp
+    with HasCoreData {
   val nack = Bool() // comes 2 cycles after req.fire
   val replay = Bool()
   val has_data = Bool()
@@ -84,7 +89,7 @@ class HellaCacheExceptions extends Bundle {
 }
 
 // interface between D$ and processor/DTLB
-class HellaCacheIO extends CoreBundle {
+class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
   val req = Decoupled(new HellaCacheReq)
   val resp = Valid(new HellaCacheResp).flip
   val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
@@ -93,50 +98,51 @@ class HellaCacheIO extends CoreBundle {
   val ordered = Bool(INPUT)
 }
 
-class L1DataReadReq extends L1HellaCacheBundle {
+class L1DataReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
   val way_en = Bits(width = nWays)
   val addr   = Bits(width = untagBits)
 }
 
-class L1DataWriteReq extends L1DataReadReq {
+class L1DataWriteReq(implicit p: Parameters) extends L1DataReadReq()(p) {
   val wmask  = Bits(width = rowWords)
   val data   = Bits(width = encRowBits)
 }
 
-class L1RefillReq extends L1DataReadReq
+class L1RefillReq(implicit p: Parameters) extends L1DataReadReq()(p)
 
-class L1MetaReadReq extends MetaReadReq {
+class L1MetaReadReq(implicit p: Parameters) extends MetaReadReq {
   val tag = Bits(width = tagBits)
+  override def cloneType = new L1MetaReadReq()(p).asInstanceOf[this.type] //TODO remove
 }
 
-class L1MetaWriteReq extends 
+class L1MetaWriteReq(implicit p: Parameters) extends 
   MetaWriteReq[L1Metadata](new L1Metadata)
 
 object L1Metadata {
-  def apply(tag: Bits, coh: ClientMetadata) = {
+  def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
     val meta = Wire(new L1Metadata)
     meta.tag := tag
     meta.coh := coh
     meta
   }
 }
-class L1Metadata extends Metadata with L1HellaCacheParameters {
+class L1Metadata(implicit p: Parameters) extends Metadata()(p) with HasL1HellaCacheParameters {
   val coh = new ClientMetadata
 }
 
-class Replay extends HellaCacheReqInternal with HasCoreData
-class ReplayInternal extends HellaCacheReqInternal with HasSDQId
+class Replay(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
+class ReplayInternal(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasSDQId
 
-class MSHRReq extends Replay with HasMissInfo
-class MSHRReqInternal extends ReplayInternal with HasMissInfo
+class MSHRReq(implicit p: Parameters) extends Replay()(p) with HasMissInfo
+class MSHRReqInternal(implicit p: Parameters) extends ReplayInternal()(p) with HasMissInfo
 
-class ProbeInternal extends Probe with HasClientTransactionId
+class ProbeInternal(implicit p: Parameters) extends Probe()(p) with HasClientTransactionId
 
-class WritebackReq extends Release with CacheParameters {
+class WritebackReq(implicit p: Parameters) extends Release()(p) with HasCacheParameters {
   val way_en = Bits(width = nWays)
 }
 
-class IOMSHR(id: Int) extends L1HellaCacheModule {
+class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new HellaCacheReq).flip
     val acquire = Decoupled(new Acquire)
@@ -213,7 +219,7 @@ class IOMSHR(id: Int) extends L1HellaCacheModule {
   }
 }
 
-class MSHR(id: Int) extends L1HellaCacheModule {
+class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req_pri_val    = Bool(INPUT)
     val req_pri_rdy    = Bool(OUTPUT)
@@ -256,7 +262,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
   val (refill_cnt, refill_count_done) = Counter(io.mem_grant.valid && gnt_multi_data, refillCycles) // TODO: Zero width?
   val refill_done = io.mem_grant.valid && (!gnt_multi_data || refill_count_done)
 
-  val rpq = Module(new Queue(new ReplayInternal, params(ReplayQueueDepth)))
+  val rpq = Module(new Queue(new ReplayInternal, p(ReplayQueueDepth)))
   rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd)
   rpq.io.enq.bits := io.req_bits
   rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
@@ -362,7 +368,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
   }
 }
 
-class MSHRFile extends L1HellaCacheModule {
+class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new MSHRReq).flip
     val resp = Decoupled(new HellaCacheResp)
@@ -498,7 +504,7 @@ class MSHRFile extends L1HellaCacheModule {
   }
 }
 
-class WritebackUnit extends L1HellaCacheModule {
+class WritebackUnit(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new WritebackReq).flip
     val meta_read = Decoupled(new L1MetaReadReq)
@@ -578,7 +584,7 @@ class WritebackUnit extends L1HellaCacheModule {
   } else { io.data_resp })
 }
 
-class ProbeUnit extends L1HellaCacheModule {
+class ProbeUnit(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new ProbeInternal).flip
     val rep = Decoupled(new Release)
@@ -653,7 +659,7 @@ class ProbeUnit extends L1HellaCacheModule {
   io.wb_req.bits.way_en := way_en
 }
 
-class DataArray extends L1HellaCacheModule {
+class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val read = Decoupled(new L1DataReadReq).flip
     val write = Decoupled(new L1DataWriteReq).flip
@@ -700,18 +706,18 @@ class DataArray extends L1HellaCacheModule {
   io.write.ready := Bool(true)
 }
 
-class HellaCache extends L1HellaCacheModule {
+class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val io = new Bundle {
     val cpu = (new HellaCacheIO).flip
     val ptw = new TLBPTWIO()
     val mem = new ClientTileLinkIO
   }
  
-  require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
+  require(p(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
   require(isPow2(nSets))
   require(isPow2(nWays)) // TODO: relax this
-  require(params(RowBits) <= params(TLDataBits))
-  require(paddrBits-blockOffBits == params(TLBlockAddrBits) )
+  require(p(RowBits) <= p(TLDataBits))
+  require(paddrBits-blockOffBits == p(TLBlockAddrBits) )
   require(untagBits <= pgIdxBits)
 
   val wb = Module(new WritebackUnit)
@@ -855,7 +861,7 @@ class HellaCache extends L1HellaCacheModule {
   when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
   when (s2_valid_masked && s2_hit || s2_replay) {
     when (s2_lr) {
-      when (!lrsc_valid) { lrsc_count := params(LRSCCycles)-1 }
+      when (!lrsc_valid) { lrsc_count := p(LRSCCycles)-1 }
       lrsc_addr := s2_req.addr >> blockOffBits
     }
     when (s2_sc) {
@@ -899,7 +905,7 @@ class HellaCache extends L1HellaCacheModule {
   writeArb.io.in(0).bits.way_en :=  s3_way
 
   // replacement policy
-  val replacer = params(Replacer)()
+  val replacer = p(Replacer)()
   val s1_replaced_way_en = UIntToOH(replacer.way)
   val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
   val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
@@ -1039,7 +1045,7 @@ class HellaCache extends L1HellaCacheModule {
 }
 
 // exposes a sane decoupled request interface
-class SimpleHellaCacheIF extends Module
+class SimpleHellaCacheIF(implicit p: Parameters) extends Module
 {
   val io = new Bundle {
     val requestor = new HellaCacheIO().flip
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 084eee2f..6f1d8534 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -6,32 +6,32 @@ import Chisel._
 import uncore._
 import Util._
 
-class PTWReq extends CoreBundle {
+class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val addr = UInt(width = vpnBits)
   val prv = Bits(width = 2)
   val store = Bool()
   val fetch = Bool()
 }
 
-class PTWResp extends CoreBundle {
+class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
   val error = Bool()
   val pte = new PTE
 }
 
-class TLBPTWIO extends CoreBundle {
+class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
   val req = Decoupled(new PTWReq)
   val resp = Valid(new PTWResp).flip
   val status = new MStatus().asInput
   val invalidate = Bool(INPUT)
 }
 
-class DatapathPTWIO extends CoreBundle {
+class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
   val ptbr = UInt(INPUT, paddrBits)
   val invalidate = Bool(INPUT)
   val status = new MStatus().asInput
 }
 
-class PTE extends CoreBundle {
+class PTE(implicit p: Parameters) extends CoreBundle()(p) {
   val ppn = Bits(width = ppnBits)
   val reserved_for_software = Bits(width = 3)
   val d = Bool()
@@ -51,8 +51,7 @@ class PTE extends CoreBundle {
     Mux(prv(0), Mux(fetch, sx(), Mux(store, sw(), sr())), Mux(fetch, ux(), Mux(store, uw(), ur())))
 }
 
-class PTW(n: Int) extends CoreModule
-{
+class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
     val requestor = Vec(new TLBPTWIO, n).flip
     val mem = new HellaCacheIO
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index ed962e26..0cfa5b53 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -20,24 +20,21 @@ class RoCCInstruction extends Bundle
   val opcode = Bits(width = 7)
 }
 
-class RoCCCommand extends CoreBundle
-{
+class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
   val inst = new RoCCInstruction
   val rs1 = Bits(width = xLen)
   val rs2 = Bits(width = xLen)
 }
 
-class RoCCResponse extends CoreBundle
-{
+class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
   val rd = Bits(width = 5)
   val data = Bits(width = xLen)
 }
 
-class RoCCInterface extends Bundle
-{
+class RoCCInterface(implicit p: Parameters) extends Bundle {
   val cmd = Decoupled(new RoCCCommand).flip
   val resp = Decoupled(new RoCCResponse)
-  val mem = new HellaCacheIO
+  val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
   val busy = Bool(OUTPUT)
   val s = Bool(INPUT)
   val interrupt = Bool(OUTPUT)
@@ -51,15 +48,12 @@ class RoCCInterface extends Bundle
   val exception = Bool(INPUT)
 }
 
-abstract class RoCC extends CoreModule
-{
+abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
   val io = new RoCCInterface
   io.mem.req.bits.phys := Bool(true) // don't perform address translation
 }
 
-class AccumulatorExample extends RoCC
-{
-  val n = 4
+class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
   val regfile = Mem(UInt(width = xLen), n)
   val busy = Reg(init=Vec(Bool(false), n))
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 30e33d0e..6ff5a414 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -7,10 +7,9 @@ import junctions._
 import uncore._
 import Util._
 
-case object BuildFPU extends Field[Option[() => FPU]]
+case object BuildFPU extends Field[Option[Parameters => FPU]]
 case object FDivSqrt extends Field[Boolean]
 case object XLen extends Field[Int]
-case object NMultXpr extends Field[Int]
 case object FetchWidth extends Field[Int]
 case object RetireWidth extends Field[Int]
 case object UseVM extends Field[Boolean]
@@ -23,59 +22,65 @@ case object CoreDataBits extends Field[Int]
 case object CoreDCacheReqTagBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
 
-abstract trait CoreParameters extends UsesParameters {
-  val xLen = params(XLen)
-  val paddrBits = params(PAddrBits)
-  val vaddrBits = params(VAddrBits)
-  val pgIdxBits = params(PgIdxBits)
-  val ppnBits = params(PPNBits)
-  val vpnBits = params(VPNBits)
-  val pgLevels = params(PgLevels)
-  val pgLevelBits = params(PgLevelBits)
-  val asIdBits = params(ASIdBits)
+trait HasCoreParameters {
+  implicit val p: Parameters
+  val xLen = p(XLen)
+  val paddrBits = p(PAddrBits)
+  val vaddrBits = p(VAddrBits)
+  val pgIdxBits = p(PgIdxBits)
+  val ppnBits = p(PPNBits)
+  val vpnBits = p(VPNBits)
+  val pgLevels = p(PgLevels)
+  val pgLevelBits = p(PgLevelBits)
+  val asIdBits = p(ASIdBits)
 
-  val retireWidth = params(RetireWidth)
-  val coreFetchWidth = params(FetchWidth)
-  val coreInstBits = params(CoreInstBits)
+  val retireWidth = p(RetireWidth)
+  val fetchWidth = p(FetchWidth)
+  val coreInstBits = p(CoreInstBits)
   val coreInstBytes = coreInstBits/8
   val coreDataBits = xLen
   val coreDataBytes = coreDataBits/8
-  val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
+  val coreDCacheReqTagBits = p(CoreDCacheReqTagBits)
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
   val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
-  val mmioBase = params(MMIOBase)
+  val mmioBase = p(MMIOBase)
+  val nCustomMrwCsrs = p(NCustomMRWCSRs)
+
+  val usingVM = p(UseVM)
+  val usingFPU = !p(BuildFPU).isEmpty
+  val usingFDivSqrt = p(FDivSqrt)
+  val usingRoCC = !p(BuildRoCC).isEmpty
+  val usingFastMulDiv = p(FastMulDiv)
+  val fastLoadWord = p(FastLoadWord)
+  val fastLoadByte = p(FastLoadByte)
 
   // Print out log of committed instructions and their writeback values.
   // Requires post-processing due to out-of-order writebacks.
-  val EnableCommitLog = false
+  val enableCommitLog = false
+  val usingPerfCounters = p(UsePerfCounters)
 
-  if(params(FastLoadByte)) require(params(FastLoadWord))
+  if (fastLoadByte) require(fastLoadWord)
 }
 
-abstract trait RocketCoreParameters extends CoreParameters
-{
-  require(params(FetchWidth) == 1)  // for now...
-  require(params(RetireWidth) == 1) // for now...
-}
+abstract class CoreModule(implicit val p: Parameters) extends Module
+  with HasCoreParameters
+abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
+  with HasCoreParameters
 
-abstract class CoreBundle extends Bundle with CoreParameters
-abstract class CoreModule extends Module with CoreParameters
-
-class Rocket extends CoreModule
-{
+class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
-    val host = new HTIFIO
-    val imem  = new CPUFrontendIO
-    val dmem = new HellaCacheIO
+    val host = new HtifIO
+    val imem  = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
+    val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
     val ptw = new DatapathPTWIO().flip
     val fpu = new FPUIO().flip
     val rocc = new RoCCInterface().flip
   }
 
   var decode_table = XDecode.table
-  if (!params(BuildFPU).isEmpty) decode_table ++= FDecode.table
-  if (!params(BuildFPU).isEmpty && params(FDivSqrt)) decode_table ++= FDivSqrtDecode.table
-  if (!params(BuildRoCC).isEmpty) decode_table ++= RoCCDecode.table
+  if (usingFPU) decode_table ++= FDecode.table
+  if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
+  if (usingRoCC) decode_table ++= RoCCDecode.table
 
   val ex_ctrl = Reg(new IntCtrlSigs)
   val mem_ctrl = Reg(new IntCtrlSigs)
@@ -123,7 +128,7 @@ class Rocket extends CoreModule
 
   // decode stage
   val id_pc = io.imem.resp.bits.pc
-  val id_inst = io.imem.resp.bits.data(0).toBits; require(params(FetchWidth) == 1)
+  val id_inst = io.imem.resp.bits.data(0).toBits; require(fetchWidth == 1)
   val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst, decode_table)
   val id_raddr3 = id_inst(31,27)
   val id_raddr2 = id_inst(24,20)
@@ -156,7 +161,7 @@ class Rocket extends CoreModule
   val id_amo_rl = id_inst(25)
   val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
   val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
-  val id_rocc_busy = Bool(!params(BuildRoCC).isEmpty) &&
+  val id_rocc_busy = Bool(usingRoCC) &&
     (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
      mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
   id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
@@ -169,8 +174,8 @@ class Rocket extends CoreModule
     (id_illegal_insn,           UInt(Causes.illegal_instruction))))
 
   val dcache_bypass_data =
-    if(params(FastLoadByte)) io.dmem.resp.bits.data
-    else if(params(FastLoadWord)) io.dmem.resp.bits.data_word_bypass
+    if (fastLoadByte) io.dmem.resp.bits.data
+    else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
     else wb_reg_wdata
 
   // detect bypass opportunities
@@ -207,8 +212,9 @@ class Rocket extends CoreModule
   alu.io.in1 := ex_op1.toUInt
   
   // multiplier and divider
-  val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1,
-                       earlyOut = params(FastMulDiv)))
+  val div = Module(new MulDiv(width = xLen,
+                              unroll = if(usingFastMulDiv) 8 else 1,
+                              earlyOut = usingFastMulDiv))
   div.io.req.valid := ex_reg_valid && ex_ctrl.div
   div.io.req.bits.dw := ex_ctrl.alu_dw
   div.io.req.bits.fn := ex_ctrl.alu_fn
@@ -345,7 +351,7 @@ class Rocket extends CoreModule
   val ll_wdata = Wire(init = div.io.resp.bits.data)
   val ll_waddr = Wire(init = div.io.resp.bits.tag)
   val ll_wen = Wire(init = div.io.resp.fire())
-  if (!params(BuildRoCC).isEmpty) {
+  if (usingRoCC) {
     io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
     when (io.rocc.resp.fire()) {
       div.io.resp.ready := Bool(false)
@@ -356,7 +362,7 @@ class Rocket extends CoreModule
   }
   when (dmem_resp_replay && dmem_resp_xpu) {
     div.io.resp.ready := Bool(false)
-    if (!params(BuildRoCC).isEmpty)
+    if (usingRoCC)
       io.rocc.resp.ready := Bool(false)
     ll_waddr := dmem_resp_waddr
     ll_wen := Bool(true)
@@ -410,7 +416,7 @@ class Rocket extends CoreModule
 
   // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
   val mem_mem_cmd_bh =
-    if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass
+    if (fastLoadWord) Bool(!fastLoadByte) && mem_reg_slow_bypass
     else Bool(true)
   val mem_cannot_bypass = mem_ctrl.csr != CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc
   val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
@@ -423,7 +429,7 @@ class Rocket extends CoreModule
   val fp_data_hazard_wb = wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
   val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
 
-  val id_stall_fpu = if (!params(BuildFPU).isEmpty) {
+  val id_stall_fpu = if (usingFPU) {
     val fp_sboard = new Scoreboard(32)
     fp_sboard.set((wb_dcache_miss && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
     fp_sboard.clear(dmem_resp_replay && dmem_resp_fpu, dmem_resp_waddr)
@@ -436,7 +442,7 @@ class Rocket extends CoreModule
     id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
     id_ctrl.fp && id_stall_fpu ||
     id_ctrl.mem && !io.dmem.req.ready ||
-    Bool(!params(BuildRoCC).isEmpty) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
+    Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
     id_do_fence ||
     csr.io.csr_stall
   ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || csr.io.interrupt
@@ -488,7 +494,7 @@ class Rocket extends CoreModule
   io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(vaddrBits-1,0)).toUInt
   io.dmem.req.bits.tag := Cat(ex_waddr, ex_ctrl.fp)
   io.dmem.req.bits.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
-  require(params(CoreDCacheReqTagBits) >= 6)
+  require(p(CoreDCacheReqTagBits) >= 6)
   io.dmem.invalidate_lr := wb_xcpt
 
   io.rocc.cmd.valid := wb_rocc_val
@@ -498,7 +504,7 @@ class Rocket extends CoreModule
   io.rocc.cmd.bits.rs1 := wb_reg_wdata
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
 
-  if (EnableCommitLog) {
+  if (enableCommitLog) {
     val pc = Wire(SInt(width=64))
     pc := wb_reg_pc
     val inst = wb_reg_inst
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index bfd8ebd8..623c64fc 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -11,22 +11,27 @@ case object NDCachePorts extends Field[Int]
 case object NPTWPorts extends Field[Int]
 case object BuildRoCC extends Field[Option[() => RoCC]]
 
-abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
+abstract class Tile(resetSignal: Bool = null)
+                   (implicit p: Parameters) extends Module(_reset = resetSignal) {
   val io = new Bundle {
     val cached = new ClientTileLinkIO
     val uncached = new ClientUncachedTileLinkIO
-    val host = new HTIFIO
+    val host = new HtifIO
   }
 }
 
-class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
-  val icache = Module(new Frontend, { case CacheName => "L1I"; case CoreName => "Rocket" })
-  val dcache = Module(new HellaCache, { case CacheName => "L1D" })
-  val ptw = Module(new PTW(params(NPTWPorts)))
-  val core = Module(new Rocket, { case CoreName => "Rocket" })
+class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) {
+  //TODO
+  val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
+  val icache = Module(new Frontend()(p.alterPartial({
+                 case CacheName => "L1I"
+                 case CoreName => "Rocket" })))
+  val dcache = Module(new HellaCache()(dcacheParams))
+  val ptw = Module(new PTW(p(NPTWPorts))(dcacheParams))
+  val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" })))
 
   dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
-  val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
+  val dcArb = Module(new HellaCacheArbiter(p(NDCachePorts))(dcacheParams))
   dcArb.io.requestor(0) <> ptw.io.mem
   dcArb.io.requestor(1) <> core.io.dmem
   dcache.io.cpu <> dcArb.io.mem
@@ -39,20 +44,16 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
   core.io.ptw <> ptw.io.dpath
 
   //If so specified, build an FPU module and wire it in
-  params(BuildFPU)
-    .map { bf => bf() }
-    .foreach { fpu =>
-      core.io.fpu <> fpu.io
-    }
+  p(BuildFPU) foreach { fpu => core.io.fpu <> fpu(p).io }
 
   // Connect the caches and ROCC to the outer memory system
   io.cached <> dcache.io.mem
   // If so specified, build an RoCC module and wire it in
   // otherwise, just hookup the icache
-  io.uncached <> params(BuildRoCC).map { buildItHere =>
+  io.uncached <> p(BuildRoCC).map { buildItHere =>
     val rocc = buildItHere()
     val memArb = Module(new ClientTileLinkIOArbiter(3))
-    val dcIF = Module(new SimpleHellaCacheIF)
+    val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
     core.io.rocc <> rocc.io
     dcIF.io.requestor <> rocc.io.mem
     dcArb.io.requestor(2) <> dcIF.io.cache
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 478dd8f2..799c869b 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -9,17 +9,19 @@ import scala.math._
 
 case object NTLBEntries extends Field[Int]
 
-abstract trait TLBParameters extends CoreParameters {
-  val addrMap = new AddrHashMap(params(NastiAddrMap))
-  val entries = params(NTLBEntries)
+trait HasTLBParameters extends HasCoreParameters {
+  val addrMap = new AddrHashMap(p(NastiAddrMap))
+  val entries = p(NTLBEntries)
   val camAddrBits = ceil(log(entries)/log(2)).toInt
   val camTagBits = asIdBits + vpnBits
 }
 
-abstract class TLBBundle extends Bundle with TLBParameters
-abstract class TLBModule extends Module with TLBParameters
+abstract class TLBModule(implicit val p: Parameters) extends Module
+  with HasTLBParameters
+abstract class TLBBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
+  with HasTLBParameters
 
-class CAMIO extends TLBBundle {
+class CAMIO(implicit p: Parameters) extends TLBBundle()(p) {
     val clear        = Bool(INPUT)
     val clear_mask   = Bits(INPUT, entries)
     val tag          = Bits(INPUT, camTagBits)
@@ -32,7 +34,7 @@ class CAMIO extends TLBBundle {
     val write_addr    = UInt(INPUT, camAddrBits)
 }
 
-class RocketCAM extends TLBModule {
+class RocketCAM(implicit p: Parameters) extends TLBModule()(p) {
   val io = new CAMIO
   val cam_tags = Mem(entries, Bits(width = camTagBits))
 
@@ -75,7 +77,7 @@ class PseudoLRU(n: Int)
   }
 }
 
-class TLBReq extends CoreBundle {
+class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
   val asid = UInt(width = asIdBits)
   val vpn = UInt(width = vpnBits+1)
   val passthrough = Bool()
@@ -83,7 +85,7 @@ class TLBReq extends CoreBundle {
   val store = Bool()
 }
 
-class TLBRespNoHitIndex extends CoreBundle {
+class TLBRespNoHitIndex(implicit p: Parameters) extends CoreBundle()(p) {
   // lookup responses
   val miss = Bool(OUTPUT)
   val ppn = UInt(OUTPUT, ppnBits)
@@ -92,11 +94,11 @@ class TLBRespNoHitIndex extends CoreBundle {
   val xcpt_if = Bool(OUTPUT)
 }
 
-class TLBResp extends TLBRespNoHitIndex with TLBParameters {
+class TLBResp(implicit p: Parameters) extends TLBRespNoHitIndex()(p) with HasTLBParameters {
   val hit_idx = UInt(OUTPUT, entries)
 }
 
-class TLB extends TLBModule {
+class TLB(implicit p: Parameters) extends TLBModule()(p) {
   val io = new Bundle {
     val req = Decoupled(new TLBReq).flip
     val resp = new TLBResp
@@ -177,7 +179,7 @@ class TLB extends TLBModule {
   io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
   io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
   io.resp.miss := tlb_miss
-  io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
+  io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(ppnBits-1,0))
   io.resp.hit_idx := tag_cam.io.hits
 
   // clear invalid entries on access, or all entries on a TLB flush

From 8173695800f9ae682189a5b14621d1dc0f68ac18 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 6 Oct 2015 18:20:19 -0700
Subject: [PATCH 30/35] added HasAddrMapParameters

---
 rocket/src/main/scala/btb.scala    |  2 +-
 rocket/src/main/scala/rocket.scala | 10 +---------
 rocket/src/main/scala/tlb.scala    |  3 +--
 3 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index d0f51e6d..8aa64112 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -10,7 +10,7 @@ case object BtbKey extends Field[BtbParameters]
 case class BtbParameters(nEntries: Int = 62, nRAS: Int = 2, updatesOutOfOrder: Boolean = false)
 
 abstract trait HasBtbParameters extends HasCoreParameters {
-  val matchBits = p(PgIdxBits)
+  val matchBits = pgIdxBits
   val entries = p(BtbKey).nEntries
   val nRAS = p(BtbKey).nRAS
   val updatesOutOfOrder = p(BtbKey).updatesOutOfOrder
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 6ff5a414..6f084aac 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -22,17 +22,9 @@ case object CoreDataBits extends Field[Int]
 case object CoreDCacheReqTagBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
 
-trait HasCoreParameters {
+trait HasCoreParameters extends HasAddrMapParameters {
   implicit val p: Parameters
   val xLen = p(XLen)
-  val paddrBits = p(PAddrBits)
-  val vaddrBits = p(VAddrBits)
-  val pgIdxBits = p(PgIdxBits)
-  val ppnBits = p(PPNBits)
-  val vpnBits = p(VPNBits)
-  val pgLevels = p(PgLevels)
-  val pgLevelBits = p(PgLevelBits)
-  val asIdBits = p(ASIdBits)
 
   val retireWidth = p(RetireWidth)
   val fetchWidth = p(FetchWidth)
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 799c869b..eb6b72ce 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -9,8 +9,7 @@ import scala.math._
 
 case object NTLBEntries extends Field[Int]
 
-trait HasTLBParameters extends HasCoreParameters {
-  val addrMap = new AddrHashMap(p(NastiAddrMap))
+trait HasTLBParameters extends HasAddrMapParameters {
   val entries = p(NTLBEntries)
   val camAddrBits = ceil(log(entries)/log(2)).toInt
   val camTagBits = asIdBits + vpnBits

From 4508666d964d8948af01bfeb3000d0827ef4760f Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 6 Oct 2015 18:22:23 -0700
Subject: [PATCH 31/35] log2ceil

---
 rocket/src/main/scala/tlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index eb6b72ce..ee624896 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -11,7 +11,7 @@ case object NTLBEntries extends Field[Int]
 
 trait HasTLBParameters extends HasAddrMapParameters {
   val entries = p(NTLBEntries)
-  val camAddrBits = ceil(log(entries)/log(2)).toInt
+  val camAddrBits = log2Ceil(entries)
   val camTagBits = asIdBits + vpnBits
 }
 

From 68cb54bc6818482cb4982f0e0426accac31da1f3 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 13 Oct 2015 23:42:53 -0700
Subject: [PATCH 32/35] refactor tilelink params

---
 rocket/src/main/scala/icache.scala   |  5 +++--
 rocket/src/main/scala/nbdcache.scala | 11 ++++++-----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index b7f2c565..de3c1fd4 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -5,8 +5,9 @@ import uncore._
 import Util._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
-  val outerDataBeats = p(TLDataBeats)
-  val outerDataBits = p(TLDataBits)
+  val outerDataBeats = p(TLKey(p(TLId))).dataBeats
+  val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
+  val outerAddrBits = p(TLKey(p(TLId))).addrBits
   val refillCyclesPerBeat = outerDataBits/rowBits
   val refillCycles = refillCyclesPerBeat*outerDataBeats
 }
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index d71cbf8f..111accef 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -18,7 +18,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
   val wordBits = p(WordBits)
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
-  val beatBytes = p(CacheBlockBytes) / p(TLDataBeats)
+  val beatBytes = p(CacheBlockBytes) / outerDataBeats
   val beatWords = beatBytes / wordBytes
   val beatOffBits = log2Up(beatBytes)
   val idxMSB = untagBits-1
@@ -32,6 +32,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
   val sdqDepth = p(StoreDataQueueDepth)
   val nMSHRs = p(NMSHRs)
   val nIOMSHRs = p(NIOMSHRs)
+  val lrscCycles = p(LRSCCycles)
 }
 
 abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
@@ -713,11 +714,11 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     val mem = new ClientTileLinkIO
   }
  
-  require(p(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
+  require(lrscCycles >= 32) // ISA requires 16-insn LRSC sequences to succeed
   require(isPow2(nSets))
   require(isPow2(nWays)) // TODO: relax this
-  require(p(RowBits) <= p(TLDataBits))
-  require(paddrBits-blockOffBits == p(TLBlockAddrBits) )
+  require(rowBits <= outerDataBits)
+  require(paddrBits-blockOffBits == outerAddrBits)
   require(untagBits <= pgIdxBits)
 
   val wb = Module(new WritebackUnit)
@@ -861,7 +862,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
   when (s2_valid_masked && s2_hit || s2_replay) {
     when (s2_lr) {
-      when (!lrsc_valid) { lrsc_count := p(LRSCCycles)-1 }
+      when (!lrsc_valid) { lrsc_count := lrscCycles-1 }
       lrsc_addr := s2_req.addr >> blockOffBits
     }
     when (s2_sc) {

From 969ecaecf8222748845d68e060857635060a15ca Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Wed, 14 Oct 2015 14:16:47 -0700
Subject: [PATCH 33/35] pass parameters to BuildRoCC

---
 rocket/src/main/scala/tile.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 623c64fc..b3419866 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -9,7 +9,7 @@ import Util._
 case object CoreName extends Field[String]
 case object NDCachePorts extends Field[Int]
 case object NPTWPorts extends Field[Int]
-case object BuildRoCC extends Field[Option[() => RoCC]]
+case object BuildRoCC extends Field[Option[Parameters => RoCC]]
 
 abstract class Tile(resetSignal: Bool = null)
                    (implicit p: Parameters) extends Module(_reset = resetSignal) {
@@ -51,7 +51,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
   // If so specified, build an RoCC module and wire it in
   // otherwise, just hookup the icache
   io.uncached <> p(BuildRoCC).map { buildItHere =>
-    val rocc = buildItHere()
+    val rocc = buildItHere(p)
     val memArb = Module(new ClientTileLinkIOArbiter(3))
     val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
     core.io.rocc <> rocc.io

From 1441590c3bb91ffca5ccee2218fa7c69a543c790 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Fri, 16 Oct 2015 19:11:57 -0700
Subject: [PATCH 34/35] add enabled field to BTBParameters

---
 rocket/src/main/scala/btb.scala | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 8aa64112..84295f27 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -7,7 +7,12 @@ import junctions._
 import Util._
 
 case object BtbKey extends Field[BtbParameters]
-case class BtbParameters(nEntries: Int = 62, nRAS: Int = 2, updatesOutOfOrder: Boolean = false)
+
+case class BtbParameters(
+  enabled: Boolean = true,
+  nEntries: Int = 62,
+  nRAS: Int = 2,
+  updatesOutOfOrder: Boolean = false)
 
 abstract trait HasBtbParameters extends HasCoreParameters {
   val matchBits = pgIdxBits

From 6f8997bee9b7e975416e06bb76272a7f8cfd690b Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Fri, 16 Oct 2015 19:12:21 -0700
Subject: [PATCH 35/35] Minor refactor of StoreGen/AMOALU.

---
 rocket/src/main/scala/nbdcache.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 111accef..19e898ec 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -161,8 +161,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val req_cmd_sc = req.cmd === M_XSC
   val grant_word = Reg(UInt(width = wordBits))
 
-  val storegen = new StoreGen(req.typ, req.addr, req.data)
-  val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc)
+  val storegen = new StoreGen64(req.typ, req.addr, req.data)
+  val loadgen = new LoadGen64(req.typ, req.addr, grant_word, req_cmd_sc)
 
   val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
   val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
@@ -992,7 +992,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   // load data subword mux/sign extension
   val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
   val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
-  val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
+  val loadgen = new LoadGen64(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
   
   amoalu.io.addr := s2_req.addr
   amoalu.io.cmd := s2_req.cmd