diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index c009c691..09bdbce1 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -28,8 +28,7 @@ class BasePlatformConfig extends Config (
       new AddrMap(entries)
     }
     lazy val externalAddrMap = new AddrMap(
-      site(ExtraDevices).map(_.addrMapEntry) ++
-      site(ExtMMIOPorts),
+      site(ExtIOAddrMapEntries),
       start = BigInt("50000000", 16),
       collapse = true)
     lazy val globalAddrMap = {
@@ -126,6 +125,8 @@ class BasePlatformConfig extends Config (
       case ExtraDevices => Nil
       case ExtraTopPorts => (p: Parameters) => new Bundle
       case ExtMMIOPorts => Nil
+      case ExtIOAddrMapEntries =>
+        site(ExtraDevices).map(_.addrMapEntry) ++ site(ExtMMIOPorts)
       case NExtMMIOAXIChannels => 0
       case NExtMMIOAHBChannels => 0
       case NExtMMIOTLChannels  => 0
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index dae6a157..26a828ac 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -38,6 +38,7 @@ case object AsyncMemChannels extends Field[Boolean]
 case object AsyncMMIOChannels extends Field[Boolean]
 /** External address map settings */
 case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
+case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
 /** Function for building Coreplex */
 case object BuildCoreplex extends Field[Parameters => Coreplex]
 /** Function for connecting coreplex extra ports to top-level extra ports */