riscv/rocket-chip
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compartmentalize Top into periphery traits

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This commit is contained in:
Yunsup Lee
2016-09-08 02:08:57 -07:00
parent 8536a2a47d
commit 2c000a99da
5 changed files with 328 additions and 310 deletions
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3
src/main/scala/rocketchip/TestHarness.scala
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@ -11,7 +11,7 @@ class TestHarness(implicit p: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
val dut = Module(new Top(p))
val dut = uncore.tilelink2.LazyModule(new ExampleTop(p)).module
// This test harness isn't especially flexible yet
require(dut.io.mem_clk.isEmpty)
@ -24,7 +24,6 @@ class TestHarness(implicit p: Parameters) extends Module {
require(dut.io.mmio_rst.isEmpty)
require(dut.io.mmio_ahb.isEmpty)
require(dut.io.mmio_tl.isEmpty)
require(dut.io.extra.elements.isEmpty)
for (int <- dut.io.interrupts)
int := false