compartmentalize Top into periphery traits
This commit is contained in:
Yunsup Lee
276
src/main/scala/rocketchip/Periphery.scala
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276
src/main/scala/rocketchip/Periphery.scala
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import uncore.converters._
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import uncore.devices._
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import uncore.util._
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import rocket.Util._
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import coreplex._
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/** Options for memory bus interface */
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object BusType {
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sealed trait EnumVal
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case object AXI extends EnumVal
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case object AHB extends EnumVal
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case object TL extends EnumVal
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val busTypes = Seq(AXI, AHB, TL)
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}
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/** Memory channel controls */
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case object TMemoryChannels extends Field[BusType.EnumVal]
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/** External MMIO controls */
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case object NExtMMIOAXIChannels extends Field[Int]
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case object NExtMMIOAHBChannels extends Field[Int]
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case object NExtMMIOTLChannels extends Field[Int]
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/** External Bus controls */
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case object NExtBusAXIChannels extends Field[Int]
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/** Async configurations */
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case object AsyncBusChannels extends Field[Boolean]
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case object AsyncDebugBus extends Field[Boolean]
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case object AsyncMemChannels extends Field[Boolean]
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case object AsyncMMIOChannels extends Field[Boolean]
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/** External address map settings */
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case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[Parameters => Coreplex]
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/** Function for connecting coreplex extra ports to top-level extra ports */
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case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
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/** Specifies the size of external memory */
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case object ExtMemSize extends Field[Long]
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/** Specifies the actual sorce of External Interrupts as Top and Periphery.
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* NExtInterrupts = NExtTopInterrupts + NExtPeripheryInterrupts
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**/
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case object NExtTopInterrupts extends Field[Int]
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case object NExtPeripheryInterrupts extends Field[Int]
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/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
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case object RTCPeriod extends Field[Int]
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object PeripheryUtils {
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def addQueueAXI(source: NastiIO)(implicit p: Parameters) = {
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val sink = Wire(new NastiIO)
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sink.ar <> Queue(source.ar, 1)
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sink.aw <> Queue(source.aw, 1)
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sink.w <> Queue(source.w)
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source.r <> Queue(sink.r)
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source.b <> Queue(sink.b, 1)
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sink
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}
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def convertTLtoAXI(tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val bridge = Module(new NastiIOTileLinkIOConverter())
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bridge.io.tl <> tl
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addQueueAXI(bridge.io.nasti)
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}
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def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean)(implicit p: Parameters) = {
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val bridge = Module(new AHBBridge(atomics))
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bridge.io.tl <> tl
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bridge.io.ahb
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}
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}
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/** Utility trait for quick access to some relevant parameters */
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trait HasPeripheryParameters {
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implicit val p: Parameters
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lazy val tMemChannels = p(TMemoryChannels)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
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lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
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lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val innerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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}
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/////
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trait PeripheryDebug extends LazyModule {
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implicit val p: Parameters
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}
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trait PeripheryDebugBundle {
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implicit val p: Parameters
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val debug_clk = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Clock(INPUT))
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val debug_rst = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Bool(INPUT))
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
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val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
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}
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trait PeripheryDebugModule {
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implicit val p: Parameters
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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val coreplex: Coreplex
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if (p(IncludeJtagDTM)) {
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// JtagDTMWithSync is a wrapper which
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// handles the synchronization as well.
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val dtm = Module (new JtagDTMWithSync()(p))
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dtm.io.jtag <> io.jtag.get
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coreplex.io.debug <> dtm.io.debug
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} else {
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coreplex.io.debug <>
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(if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug.get)
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else io.debug.get)
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}
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}
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/////
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trait PeripheryInterrupt extends LazyModule {
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implicit val p: Parameters
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}
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trait PeripheryInterruptBundle {
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implicit val p: Parameters
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val interrupts = Vec(p(NExtTopInterrupts), Bool()).asInput
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}
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trait PeripheryInterruptModule {
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implicit val p: Parameters
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val outer: PeripheryInterrupt
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val io: PeripheryInterruptBundle
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val coreplex: Coreplex
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val interrupts_periphery = Vec(p(NExtPeripheryInterrupts), Bool())
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var interrupts_cnt = 0
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// This places the Periphery Interrupts at Bits [0...]
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// External interrupts are at the higher Bits.
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// This may have some implications for prioritization of the interrupts,
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// but PLIC could do some internal swizzling in the future.
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coreplex.io.interrupts <> (interrupts_periphery ++ io.interrupts)
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}
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/////
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trait PeripheryMasterMem extends LazyModule {
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implicit val p: Parameters
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}
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trait PeripheryMasterMemBundle extends HasPeripheryParameters {
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implicit val p: Parameters
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val mem_clk = p(AsyncMemChannels).option(Vec(nMemChannels, Clock(INPUT)))
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val mem_rst = p(AsyncMemChannels).option(Vec(nMemChannels, Bool (INPUT)))
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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}
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trait PeripheryMasterMemModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryMasterMem
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val io: PeripheryMasterMemBundle
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val coreplex: Coreplex
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// Abuse the fact that zip takes the shorter of the two lists
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((io.mem_axi zip coreplex.io.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
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val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
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axi_sync.ar.bits.cache := UInt("b0011")
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axi_sync.aw.bits.cache := UInt("b0011")
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axi <> (
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if (!p(AsyncMemChannels)) axi_sync
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else AsyncNastiTo(io.mem_clk.get(idx), io.mem_rst.get(idx), axi_sync)
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)
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}
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(io.mem_ahb zip coreplex.io.mem) foreach { case (ahb, mem) =>
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ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)(outermostParams)
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}
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(io.mem_tl zip coreplex.io.mem) foreach { case (tl, mem) =>
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tl <> ClientUncachedTileLinkEnqueuer(mem, 2)(outermostParams)
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}
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}
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/////
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trait PeripheryMasterMMIO extends LazyModule {
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implicit val p: Parameters
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}
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trait PeripheryMasterMMIOBundle extends HasPeripheryParameters {
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implicit val p: Parameters
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val mmio_clk = p(AsyncMMIOChannels).option(Vec(p(NExtMMIOAXIChannels), Clock(INPUT)))
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val mmio_rst = p(AsyncMMIOChannels).option(Vec(p(NExtMMIOAXIChannels), Bool (INPUT)))
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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}
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trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryMasterMMIO
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val io: PeripheryMasterMMIOBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val mmio_ports = p(ExtMMIOPorts) map { port =>
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TileLinkWidthAdapter(mmioNetwork.get.port(port.name), "MMIO_Outermost")
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}
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val mmio_axi_start = 0
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val mmio_axi_end = mmio_axi_start + p(NExtMMIOAXIChannels)
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val mmio_ahb_start = mmio_axi_end
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val mmio_ahb_end = mmio_ahb_start + p(NExtMMIOAHBChannels)
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val mmio_tl_start = mmio_ahb_end
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val mmio_tl_end = mmio_tl_start + p(NExtMMIOTLChannels)
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require (mmio_tl_end == mmio_ports.size)
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for (i <- 0 until mmio_ports.size) {
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if (mmio_axi_start <= i && i < mmio_axi_end) {
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val idx = i-mmio_axi_start
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val axi_sync = PeripheryUtils.convertTLtoAXI(mmio_ports(i))(outermostMMIOParams)
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io.mmio_axi(idx) <> (
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if (!p(AsyncMMIOChannels)) axi_sync
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else AsyncNastiTo(io.mmio_clk.get(idx), io.mmio_rst.get(idx), axi_sync)
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)
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} else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
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val idx = i-mmio_ahb_start
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io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)(outermostMMIOParams)
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} else if (mmio_tl_start <= i && i < mmio_tl_end) {
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val idx = i-mmio_tl_start
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io.mmio_tl(idx) <> ClientUncachedTileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
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} else {
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require(false, "Unconnected external MMIO port")
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}
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}
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}
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/////
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trait PeripherySlave extends LazyModule {
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implicit val p: Parameters
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}
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trait PeripherySlaveBundle extends HasPeripheryParameters {
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implicit val p: Parameters
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val bus_clk = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Clock(INPUT)))
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val bus_rst = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Bool (INPUT)))
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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}
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trait PeripherySlaveModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripherySlave
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val io: PeripherySlaveBundle
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val coreplex: Coreplex
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if (p(NExtBusAXIChannels) > 0) {
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val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
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((io.bus_axi zip arb.io.master) zipWithIndex) foreach { case ((bus, port), idx) =>
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port <> (
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if (!p(AsyncBusChannels)) bus
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else AsyncNastiFrom(io.bus_clk.get(idx), io.bus_rst.get(idx), bus)
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)
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}
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val conv = Module(new TileLinkIONastiIOConverter()(innerParams))
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conv.io.nasti <> arb.io.slave
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coreplex.io.ext_clients.head <> conv.io.tl
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require(p(NExternalClients) == 1, "external devices can't slave ports. wait for tilelink2!")
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}
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}
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