riscv/rocket-chip
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Use chisel3 Clock() method.

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Jim Lawson 2017-07-07 14:16:39 -07:00
parent 4c595d175c
commit 2bf91a0558
1 changed files with 1 additions and 1 deletions
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src/main/scala/jtag/JtagTap.scala
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@ -8,7 +8,7 @@ import chisel3.util._
*/ */
class JTAGIO(hasTRSTn: Boolean = false) extends Bundle { class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
val TCK = Clock(OUTPUT) val TCK = Output(Clock())
val TMS = Output(Bool()) val TMS = Output(Bool())
val TDI = Output(Bool()) val TDI = Output(Bool())
val TDO = Input(new Tristate()) val TDO = Input(new Tristate())