riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use chisel3 Clock() method.

Browse Source
This commit is contained in:
Jim Lawson
2017-07-07 14:16:39 -07:00
parent 4c595d175c
commit 2bf91a0558
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/jtag/JtagTap.scala
View File

@@ -8,7 +8,7 @@ import chisel3.util._
*/ */
class JTAGIO(hasTRSTn: Boolean = false) extends Bundle { class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
val TCK = Clock(OUTPUT) val TCK = Output(Clock())
val TMS = Output(Bool()) val TMS = Output(Bool())
val TDI = Output(Bool()) val TDI = Output(Bool())
val TDO = Input(new Tristate()) val TDO = Input(new Tristate())