riscv/rocket-chip
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Merge branch 'master' into move-to-util

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This commit is contained in:
Andrew Waterman
2016-09-29 14:42:11 -07:00
committed by GitHub
parent ab3219cf6e e928b741ce
commit 2bdf8c2be7
5 changed files with 106 additions and 30 deletions
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5
src/main/scala/rocketchip/DebugTransport.scala
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@ -55,7 +55,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
jtag_dtm.io.jtag <> io.jtag
jtag_dtm.io.jtag := io.jtag
val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
@ -73,6 +73,9 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
dtm_resp.valid := io_debug_bus.resp.valid
dtm_resp.bits := io_debug_bus.resp.bits.asUInt
io_debug_bus.resp.ready := dtm_resp.ready
dtm_req := jtag_dtm.io.dtm_req
jtag_dtm.io.dtm_resp := dtm_resp
}
class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {