riscv/rocket-chip
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Merge branch 'master' into move-to-util

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This commit is contained in:
Andrew Waterman
2016-09-29 14:42:11 -07:00
committed by GitHub
parent ab3219cf6e e928b741ce
commit 2bdf8c2be7
5 changed files with 106 additions and 30 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -100,7 +100,7 @@ class BaseCoreplexConfig extends Config (
case UseCompressed => true
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case NCustomMRWCSRs => 0
case MtvecInit => None
case MtvecInit => Some(BigInt(0))
case MtvecWritable => true
//Uncore Paramters
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients

5
src/main/scala/rocketchip/DebugTransport.scala
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@ -55,7 +55,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
jtag_dtm.io.jtag <> io.jtag
jtag_dtm.io.jtag := io.jtag
val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
@ -73,6 +73,9 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
dtm_resp.valid := io_debug_bus.resp.valid
dtm_resp.bits := io_debug_bus.resp.bits.asUInt
io_debug_bus.resp.ready := dtm_resp.ready
dtm_req := jtag_dtm.io.dtm_req
jtag_dtm.io.dtm_resp := dtm_resp
}
class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {

59
src/main/scala/uncore/devices/Debug.scala
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@ -475,16 +475,23 @@ class DebugModule ()(implicit val p:cde.Parameters)
val ramWrEn = Wire(Bool())
val dbRamAddr = Wire(UInt(width=dbRamAddrWidth))
val dbRamAddrValid = Wire(Bool())
val dbRamRdData = Wire (UInt(width=dbRamDataWidth))
val dbRamWrData = Wire(UInt(width=dbRamDataWidth))
val dbRamWrEn = Wire(Bool())
val dbRamRdEn = Wire(Bool())
val dbRamWrEnFinal = Wire(Bool())
val dbRamRdEnFinal = Wire(Bool())
val sbRamAddr = Wire(UInt(width=sbRamAddrWidth))
val sbRamAddrValid = Wire(Bool())
val sbRamRdData = Wire (UInt(width=sbRamDataWidth))
val sbRamWrData = Wire(UInt(width=sbRamDataWidth))
val sbRamWrEn = Wire(Bool())
val sbRamRdEn = Wire(Bool())
val sbRamWrEnFinal = Wire(Bool())
val sbRamRdEnFinal = Wire(Bool())
val sbRomRdData = Wire(UInt(width=tlDataBits))
val sbRomAddrOffset = log2Up(tlDataBits/8)
@ -624,8 +631,18 @@ class DebugModule ()(implicit val p:cde.Parameters)
// 0x40 - 0x6F Not Implemented
dbRamAddr := dbReq.addr( dbRamAddrWidth-1 , 0)
dbRamWrData := dbReq.data
dbRamAddrValid := Bool(true)
if (dbRamAddrWidth < 4){
dbRamAddrValid := (dbReq.addr(3, dbRamAddrWidth) === UInt(0))
}
sbRamAddr := sbAddr(sbRamAddrWidth + sbRamAddrOffset - 1, sbRamAddrOffset)
sbRamWrData := sbWrData
sbRamAddrValid := Bool(true)
// From Specification: Debug RAM is 0x400 - 0x4FF
if ((sbRamAddrWidth + sbRamAddrOffset) < 8){
sbRamAddrValid := (sbAddr(7, sbRamAddrWidth + sbRamAddrOffset) === UInt(0))
}
require (dbRamAddrWidth >= ramAddrWidth) // SB accesses less than 32 bits Not Implemented.
val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
@ -661,7 +678,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
ramRdData := ramMem(ramAddr)
when (ramWrEn) { ramMem(ramAddr) := ramWrData }
ramWrEn := sbRamWrEn | dbRamWrEn
ramWrEn := sbRamWrEnFinal | dbRamWrEnFinal
//--------------------------------------------------------------
// Debug Bus Access
@ -680,11 +697,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
CONTROLWrData := new CONTROLFields().fromBits(dbReq.data)
RAMWrData := new RAMFields().fromBits(dbReq.data)
dbRamWrEn := Bool(false)
CONTROLWrEn := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRamWrEn := Bool(false)
dbRamWrEnFinal := Bool(false)
CONTROLWrEn := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRamWrEn := dbWrEn
}.elsewhen (dbReq.addr === DMCONTROL) {
when (dbRamAddrValid) {
dbRamWrEnFinal := dbWrEn
}
}.elsewhen (dbReq.addr === DMCONTROL) {
CONTROLWrEn := dbWrEn
}.otherwise {
//Other registers/RAM are Not Implemented.
@ -739,10 +760,14 @@ class DebugModule ()(implicit val p:cde.Parameters)
}
}
dbRamRdEn := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRdData := RAMRdData.asUInt
dbRamRdEn := Bool(false)
dbRamRdEnFinal := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRamRdEn := dbRdEn
when (dbRamAddrValid) {
dbRdData := RAMRdData.asUInt
dbRamRdEnFinal := dbRdEn
}
}.elsewhen (dbReq.addr === DMCONTROL) {
dbRdData := CONTROLRdData.asUInt
}.elsewhen (dbReq.addr === DMINFO) {
@ -849,6 +874,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
// SB Access Write Decoder
sbRamWrEn := Bool(false)
sbRamWrEnFinal := Bool(false)
SETHALTNOTWrEn := Bool(false)
CLEARDEBINTWrEn := Bool(false)
@ -858,6 +884,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
when (sbAddr(11, 8) === UInt(4)){ // 0x400-0x4ff is Debug RAM
sbRamWrEn := sbWrEn
sbRamRdEn := sbRdEn
when (sbRamAddrValid) {
sbRamWrEnFinal := sbWrEn
sbRamRdEnFinal := sbRdEn
}
}.elsewhen (sbAddr === SETHALTNOT){
SETHALTNOTWrEn := sbWrEn
}.elsewhen (sbAddr === CLEARDEBINT){
@ -880,6 +910,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
when (sbAddr(11,8) === UInt(4)){ //0x400-0x4ff is Debug RAM
sbRamWrEn := sbWrEn
sbRamRdEn := sbRdEn
when (sbRamAddrValid){
sbRamWrEnFinal := sbWrEn
sbRamRdEnFinal := sbRdEn
}
}
SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
@ -896,12 +930,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
// SB Access Read Mux
sbRdData := UInt(0)
sbRamRdEn := Bool(false)
sbRamRdEn := Bool(false)
sbRamRdEnFinal := Bool(false)
dbRamRdEn := Bool(false)
when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
sbRdData := sbRamRdData
sbRamRdEn := sbRdEn
when (sbRamAddrValid) {
sbRdData := sbRamRdData
sbRamRdEnFinal := sbRdEn
}
}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
if (cfg.hasDebugRom) {
sbRdData := sbRomRdData