riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: most adapters can wipe away latency

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-09-21 18:43:09 -07:00
parent c115913624
commit 2b24c4b1b4
3 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/tilelink2/Fragmenter.scala
View File

@ -47,9 +47,10 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
supportsPutPartial = TransferSizes.none,
supportsHint = TransferSizes.none)
// Because the Fragmenter stalls inner A while serving outer, it can wipe away inner latency
val node = TLAdapterNode(
clientFn = { case Seq(c) => c.copy(clients = c.clients.map(mapClient)) },
managerFn = { case Seq(m) => m.copy(managers = m.managers.map(mapManager)) })
managerFn = { case Seq(m) => m.copy(managers = m.managers.map(mapManager), minLatency = 0) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {

5
src/main/scala/uncore/tilelink2/HintHandler.scala
View File

@ -8,9 +8,10 @@ import chisel3.internal.sourceinfo.SourceInfo
// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
{
// HintAcks can come back combinationally => minLatency=0
val node = TLAdapterNode(
clientFn = { case Seq(c) => if (!supportClients) c else c.copy(clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
managerFn = { case Seq(m) => if (!supportManagers) m else m.copy(managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
clientFn = { case Seq(c) => if (!supportClients) c else c.copy(minLatency = 0, clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
managerFn = { case Seq(m) => if (!supportManagers) m else m.copy(minLatency = 0, managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {

5
src/main/scala/uncore/tilelink2/WidthWidget.scala
View File

@ -10,9 +10,10 @@ import scala.math.{min,max}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
{
// Because we stall the request while sending beats, atomics can overlap => minLatency=0
val node = TLAdapterNode(
clientFn = { case Seq(c) => c },
managerFn = { case Seq(m) => m.copy(beatBytes = innerBeatBytes) })
clientFn = { case Seq(c) => c.copy(minLatency = 0) },
managerFn = { case Seq(m) => m.copy(minLatency = 0, beatBytes = innerBeatBytes) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {