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get rid of init_node

This commit is contained in:
Huy Vo 2013-04-20 01:36:32 -07:00
parent 0d87e3bacc
commit 2ac3fd5306

View File

@ -276,16 +276,12 @@ class ReferenceChipBackend extends VerilogBackend
def addMemPin(c: Component) = {
for (node <- Component.nodes) {
if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
val init = Bool()
init.setName("init_node")
node.inputs += init
init.component = node.component
connectMemPin(c, node.component, init)
connectMemPin(c, node.component, node)
}
}
}
def connectMemPin(topC: Component, c: Component, p: Bool): Unit = {
def connectMemPin(topC: Component, c: Component, p: Node): Unit = {
var isNewPin = false
val compInitPin =
if (initMap.contains(c)) {