get rid of init_node
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0d87e3bacc
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2ac3fd5306
@ -276,16 +276,12 @@ class ReferenceChipBackend extends VerilogBackend
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def addMemPin(c: Component) = {
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def addMemPin(c: Component) = {
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for (node <- Component.nodes) {
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for (node <- Component.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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val init = Bool()
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connectMemPin(c, node.component, node)
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init.setName("init_node")
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node.inputs += init
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init.component = node.component
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connectMemPin(c, node.component, init)
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}
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}
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}
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}
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}
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}
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def connectMemPin(topC: Component, c: Component, p: Bool): Unit = {
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def connectMemPin(topC: Component, c: Component, p: Node): Unit = {
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var isNewPin = false
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var isNewPin = false
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val compInitPin =
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val compInitPin =
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if (initMap.contains(c)) {
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if (initMap.contains(c)) {
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