Chisel implicit clock is now named clock, not clk

chisel3

@@ -1 +1 @@
-Subproject commit dda64c1dee16b5da15ac690bd3cd6759c3d5c032
+Subproject commit b18e98ba2d058c7dd24f96f005486b70c856aeca

csrc/emulator.cc

@@ -84,16 +84,16 @@ int main(int argc, char** argv)
   // reset for several cycles to handle pipelined reset
   for (int i = 0; i < 10; i++) {
     tile->reset = 1;
-    tile->clk = 0;
+    tile->clock = 0;
     tile->eval();
-    tile->clk = 1;
+    tile->clock = 1;
     tile->eval();
     tile->reset = 0;
   }
   done_reset = true;
 
   while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
-    tile->clk = 0;
+    tile->clock = 0;
     tile->eval();
 #if VM_TRACE
     bool dump = tfp && trace_count >= start;
@@ -101,7 +101,7 @@ int main(int argc, char** argv)
       tfp->dump(static_cast<vluint64_t>(trace_count * 2));
 #endif
 
-    tile->clk = 1;
+    tile->clock = 1;
     tile->eval();
 #if VM_TRACE
     if (dump)

firrtl

@@ -1 +1 @@
-Subproject commit 726c808375fe513c70376bf05e76dd938e578bf9
+Subproject commit 8b12dcbb76896a19f95dc4da19b3b8c74c1ddda3

vsrc/TestDriver.v

@@ -2,10 +2,10 @@
 
 module TestDriver;
 
-  reg clk   = 1'b0;
+  reg clock = 1'b0;
   reg reset = 1'b1;
 
-  always #(`CLOCK_PERIOD/2.0) clk = ~clk;
+  always #(`CLOCK_PERIOD/2.0) clock = ~clock;
   initial #777.7 reset = 0;
 
   // Read input arguments and initialize
@@ -48,7 +48,7 @@ module TestDriver;
   reg failure = 1'b0;
   wire success;
   integer stderr = 32'h80000002;
-  always @(posedge clk)
+  always @(posedge clock)
   begin
 `ifdef GATE_LEVEL
     if (verbose)
@@ -88,7 +88,7 @@ module TestDriver;
   end
 
   TestHarness testHarness(
-    .clk(clk),
+    .clock(clock),
     .reset(reset),
     .io_success(success)
   );