Chisel implicit clock is now named clock, not clk

vsrc/TestDriver.v

@@ -2,10 +2,10 @@
 
 module TestDriver;
 
-  reg clk   = 1'b0;
+  reg clock = 1'b0;
   reg reset = 1'b1;
 
-  always #(`CLOCK_PERIOD/2.0) clk = ~clk;
+  always #(`CLOCK_PERIOD/2.0) clock = ~clock;
   initial #777.7 reset = 0;
 
   // Read input arguments and initialize
@@ -48,7 +48,7 @@ module TestDriver;
   reg failure = 1'b0;
   wire success;
   integer stderr = 32'h80000002;
-  always @(posedge clk)
+  always @(posedge clock)
   begin
 `ifdef GATE_LEVEL
     if (verbose)
@@ -88,7 +88,7 @@ module TestDriver;
   end
 
   TestHarness testHarness(
-    .clk(clk),
+    .clock(clock),
     .reset(reset),
     .io_success(success)
   );