riscv/rocket-chip
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squash subsequent external mem request after nack

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This commit is contained in:
Andrew Waterman 2012-02-14 15:12:16 -08:00
parent 38c67e5a9e
commit 297223a13c
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/ctrl.scala
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@ -624,7 +624,7 @@ class rocketCtrl extends Component
val dmem_kill_mem = io.dpath.mem_valid && (io.dtlb_miss || io.dmem.resp_nack)
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay
val kill_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill || Reg(io.ext_mem.resp_nack)
// replay execute stage PC when the D$ is blocked, when the D$ misses,
// for privileged instructions, and for fence.i instructions