From 2961d92244f17ccd6be35ab2884ed82cc1ff3292 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 19 Sep 2016 13:46:45 -0700
Subject: [PATCH] [testharness] vsim makefrag cleanup

---
 vsim/Makefrag         |  8 ++++----
 vsim/Makefrag-verilog | 13 ++++++-------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/vsim/Makefrag b/vsim/Makefrag
index f06fc032..36606737 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -15,8 +15,8 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
 
 
 sim_vsrcs = \
-	$(generated_dir)/$(MODEL).$(CONFIG).v \
-	$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
+	$(generated_dir)/$(long_name).v \
+	$(generated_dir)/$(long_name).behav_srams.v \
 	$(generated_dir)/consts.$(CONFIG).vh \
 	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/SimDTM.v \
@@ -70,14 +70,14 @@ VCS_OPTS += -CC "-DVCS_VPI"
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
+simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
 $(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 	-debug_pp \
 
-simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
+simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index c0ab9576..12fb7678 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -1,21 +1,20 @@
 #--------------------------------------------------------------------
 # Verilog Generation
 #--------------------------------------------------------------------
+firrtl = $(generated_dir)/$(long_name).fir
+verilog = $(generated_dir)/$(long_name).v
+
 # If I don't mark these as .SECONDARY then make will delete these internal
 # files.
-.SECONDARY: $(generated_dir)/$(long_name).fir
+.SECONDARY: $(firrtl) $(verilog)
 
-firrtl: $(generated_dir)/$(long_name).fir
-
-.PHONY: firrtl
-
-$(generated_dir)/%.fir $(generated_dir)/%.d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
+$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
+	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \