Remove fsim, as it is the same as vsim, modulo CONFIG
This commit is contained in:
Andrew Waterman
parent
1b8f919db2
commit
2906c75167
@ -47,7 +47,6 @@ before_install:
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script:
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- make vsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
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- make fsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
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- make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
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- make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
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29
README.md
29
README.md
@ -72,12 +72,7 @@ And to run the assembly tests on the C simulator and generate waveforms:
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$ make -jN run-asm-tests-debug
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$ make -jN run-bmark-tests-debug
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To generate FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
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$ cd fsim
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$ make verilog
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Similarly, to generate VLSI-synthesizable verilog (output will be in `vsim/generated-src`):
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To generate FPGA- or VLSI-synthesizable verilog (output will be in `vsim/generated-src`):
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$ cd vsim
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$ make verilog
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@ -384,7 +379,7 @@ writeback stage. At cycle 485, there isn't a valid instruction in the
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writeback stage, perhaps, because of a instruction cache miss at PC
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0x2140.
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### <a name="fpga"></a> 2) Mapping a Rocket core down to an FPGA
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### <a name="fpga"></a> 2) Mapping a Rocket core to an FPGA
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We use Synopsys VCS for Verilog simulation. We acknowledge that using a
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proprietary Verilog simulation tool for an open-source project is not
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@ -395,14 +390,13 @@ Verilog simulator. In the meantime, you can use the C++ emulator to
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generate vcd waveforms, which you can view with an open-source waveform
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viewer such as GTKWave.
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So assuming you have a working Rocket chip, you can generate Verilog for
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the FPGA tools with the following commands:
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You can generate synthesizable Verilog with the following commands:
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$ cd $ROCKETCHIP/fsim
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$ make verilog
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$ cd $ROCKETCHIP/vsim
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$ make verilog CONFIG=DefaultFPGAConfig
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The Verilog used for the FPGA tools will be generated in
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fsim/generated-src. Please proceed further with the directions shown in
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vsim/generated-src. Please proceed further with the directions shown in
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the [README](https://github.com/ucb-bar/fpga-zynq/blob/master/README.md)
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of the fpga-zynq repository.
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@ -410,11 +404,11 @@ However, if you have access to VCS, you will be able to run assembly
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tests and benchmarks with the following commands (again assuming you
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have N cores on your host machine):
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$ cd $ROCKETCHIP/fsim
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$ make -jN run
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$ cd $ROCKETCHIP/vsim
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$ make -jN run CONFIG=DefaultFPGAConfig
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The generated output looks similar to those generated from the emulator.
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Look into fsim/output/\*.out for the output of the executed assembly
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Look into vsim/output/\*.out for the output of the executed assembly
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tests and benchmarks.
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### <a name="vlsi"></a> 3) Pushing a Rocket core through the VLSI tools
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@ -485,9 +479,8 @@ Towards the end, you can also find that ExampleSmallConfig inherits all
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parameters from BaseConfig but overrides the same parameters of
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SmallConfig.
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Now take a look at fsim/Makefile and vsim/Makefile. Search for the
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CONFIG variable. DefaultFPGAConfig is used for the FPGA build, while
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DefaultConfig is used for the VLSI build. You can also change the
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Now take a look at vsim/Makefile. Search for the CONFIG variable.
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By default, it is set to DefaultConfig. You can also change the
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CONFIG variable on the make command line:
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$ cd $ROCKETCHIP/vsim
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18
fsim/.gitignore
vendored
18
fsim/.gitignore
vendored
@ -1,18 +0,0 @@
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simv*
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csrc
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*.vpd
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*.key
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DVE*
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.vcs*
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timestamp
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*.out
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*.h
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*.log
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*.cmd
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*.daidir
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*.ucli
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*.a
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*.vcd
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dramsim2_ini
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generated-src
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output
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@ -1,35 +0,0 @@
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#=======================================================================
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# Makefile for Verilog simulation w/ VCS
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#-----------------------------------------------------------------------
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# Yunsup Lee (yunsup@cs.berkeley.edu)
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#
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# This makefile will build a rtl simulator and run various tests to
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# verify proper functionality.
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#
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default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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mem_gen = $(base_dir)/fsim/fpga_mem_gen
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sim_dir = .
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output_dir = $(sim_dir)/output
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BACKEND ?= v
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CONFIG ?= DefaultFPGAConfig
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TB ?= rocketTestHarness
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include $(base_dir)/Makefrag
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include $(sim_dir)/Makefrag
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ifneq ($(MAKECMDGOALS),clean)
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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endif
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include $(base_dir)/vsim/Makefrag-verilog
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all: $(simv)
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debug: $(simv_debug)
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clean:
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rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
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.PHONY: default all debug clean
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@ -1,75 +0,0 @@
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#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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$(generated_dir)/consts.$(CONFIG).vh \
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$(base_dir)/vsrc/$(TB).v \
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/vcs_main.$(TB).cc \
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$(base_dir)/csrc/mm.cc \
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$(base_dir)/csrc/mm_dramsim2.cc \
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#--------------------------------------------------------------------
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# Build Verilog
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#--------------------------------------------------------------------
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verilog: $(sim_vsrcs)
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.PHONY: verilog
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-I$(realpath $(base_dir))/dramsim2" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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+incdir+$(generated_dir) \
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+define+FPGA \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).verbose \
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+libext+.v \
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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-debug_pp \
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simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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@ -1,195 +0,0 @@
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#! /usr/bin/env python
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# See LICENSE for license details.
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# This is based off of reference-chip/vlsi/src/vlsi_mem_gen
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import sys
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import math
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use_latches = False
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module_template = '''module %s(
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%s
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);
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%s
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%s
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always @(posedge CLK) begin
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%s
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end
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%s
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endmodule
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'''
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mask_assert_template = '''
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`ifndef SYNTHESIS
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integer i;
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integer j;
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always @(posedge CLK) begin%s
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end
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`endif
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'''
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assert_template = '''
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for (i=0; i<%d; i=i+%d) begin
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for (j=1; j<%d; j=j+1) begin
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if (%sM[i] != %sM[i+j]) begin
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$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\\n");
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$finish;
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end
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end
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end'''
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def parse_line(line):
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name = ''
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width = 0
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depth = 0
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ports = ''
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mask_gran = 1
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tokens = line.split()
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i = 0
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for i in range(0,len(tokens),2):
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s = tokens[i]
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if s == 'name':
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name = tokens[i+1]
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elif s == 'width':
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width = int(tokens[i+1])
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elif s == 'depth':
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depth = int(tokens[i+1])
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elif s == 'ports':
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ports = tokens[i+1].split(',')
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elif s == 'mask_gran':
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mask_gran = int(tokens[i+1])
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else:
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sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
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return (name, width, depth, ports, mask_gran)
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def gen_range(mask_index, mask_gran, max_width):
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return '%d:%d' % (min(mask_gran*(mask_index+1),max_width)-1,
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min(mask_gran*(mask_index),max_width))
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def gen_mem(name, width, depth, ports, mask_gran):
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addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
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mask_width = int(math.ceil(float(width) / mask_gran))
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port_spec = ['input CLK', 'input RST', 'input init']
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readports = []
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writeports = []
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latchports = []
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rwports = []
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decl = []
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combinational = []
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sequential = []
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maskedports = {}
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mask_asserts = ''
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for pid in range(len(ports)):
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ptype = ports[pid]
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if ptype[0:1] == 'm':
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ptype = ptype[1:]
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maskedports[pid] = pid
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if ptype == 'read':
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port_spec += ['input [%d:0] R%dA' % (addr_width-1, pid)]
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port_spec += ['input R%dE' % pid]
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port_spec += ['output [%d:0] R%dO' % (width-1, pid)]
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readports += [pid]
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elif ptype == 'write':
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port_spec += ['input [%d:0] W%dA' % (addr_width-1, pid)]
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port_spec += ['input W%dE' % pid]
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port_spec += ['input [%d:0] W%dI' % (width-1, pid)]
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if pid in maskedports:
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port_spec += ['input [%d:0] W%dM' % (width-1, pid)]
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if not use_latches or pid in maskedports:
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writeports += [pid]
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else:
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latchports += [pid]
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elif ptype == 'rw':
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port_spec += ['input [%d:0] RW%dA' % (addr_width-1, pid)]
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port_spec += ['input RW%dE' % pid]
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port_spec += ['input RW%dW' % pid]
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if pid in maskedports:
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port_spec += ['input [%d:0] RW%dM' % (width-1, pid)]
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port_spec += ['input [%d:0] RW%dI' % (width-1, pid)]
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port_spec += ['output [%d:0] RW%dO' % (width-1, pid)]
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rwports += [pid]
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else:
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sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
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decl += ['reg [%d:0] ram [%d:0];' % (width-1, depth-1)]
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decl += ['`ifndef SYNTHESIS']
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decl += [' integer initvar;']
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decl += [' initial begin']
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decl += [' #0.002;']
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decl += [' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth]
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decl += [' ram[initvar] = {%d {$random}};' % ((width-1)/32+1)]
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decl += [' end']
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decl += ['`endif']
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for pid in readports:
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decl += ['reg [%d:0] reg_R%dA;' % (addr_width-1, pid)]
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sequential += ['if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid)]
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combinational += ['assign R%dO = ram[reg_R%dA];' % (pid, pid)]
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for pid in rwports:
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decl += ['reg [%d:0] reg_RW%dA;' % (addr_width-1, pid)]
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sequential += ['if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid)]
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combinational += ['assign RW%dO = ram[reg_RW%dA];' % (pid, pid)]
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for pid in latchports:
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decl += ['reg [%d:0] latch_W%dA;' % (addr_width-1, pid)]
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decl += ['reg [%d:0] latch_W%dI;' % (width-1, pid)]
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decl += ['reg latch_W%dE;' % (pid)]
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combinational += ['always @(*) begin']
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combinational += [' if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid)]
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combinational += [' if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid)]
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combinational += [' if (!CLK) latch_W%dE <= W%dE;' % (pid, pid)]
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combinational += ['end']
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combinational += ['always @(*)']
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combinational += [' if (CLK && latch_W%dE)' % (pid)]
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combinational += [' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid)]
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for pid in writeports:
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if pid not in maskedports:
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sequential += ['if (W%dE) ram[W%dA] <= W%dI;' % (pid, pid, pid)]
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else:
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for mask_index in range(mask_width):
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rs = gen_range(mask_index, mask_gran, width)
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sequential += ['if (W%dE && W%dM[%d]) ram[W%dA][%s] <= W%dI[%s];' %
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(pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
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mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'W'+str(pid), 'W'+str(pid))
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for pid in rwports:
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if pid not in maskedports:
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sequential += ['if (RW%dE && RW%dW) ram[RW%dA] <= RW%dI;' % (pid, pid, pid, pid)]
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else:
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for mask_index in range(mask_width):
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rs = gen_range(mask_index, mask_gran, width)
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sequential += ['if (RW%dE && RW%dW && RW%dM[%d]) ram[RW%dA][%s] <= RW%dI[%s];' %
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(pid, pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
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mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'RW'+str(pid), 'RW'+str(pid))
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check_masks = '' if len(maskedports) == 0 else mask_assert_template % mask_asserts
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return module_template % (name,
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',\n '.join(port_spec),
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check_masks,
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'\n '.join(decl),
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'\n '.join(sequential),
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'\n '.join(combinational))
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def main():
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if len(sys.argv) < 2:
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sys.exit('Please give a .conf file as input')
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for line in open(sys.argv[1]):
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print(gen_mem(*parse_line(line)))
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if __name__ == '__main__':
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main()
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@ -1,5 +1,5 @@
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# The default target, which runs all regression targets.
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regression: vsim-regression fsim-regression emulator-regression
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regression: vsim-regression emulator-regression
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# Regression targets for the various simulators.
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%-regression: %-asm-tests %-bmark-tests
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@ -36,7 +36,6 @@ include $(TOP)/Makefrag
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clean:
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rm -rf stamps $(abspath $(RISCV))
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$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/vsim) clean
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$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/fsim) clean
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$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/emulator) clean
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ifeq ($(SUITE),)
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@ -91,22 +90,6 @@ vsim-bmark-tests: $(VSIM_BMARK_TEST_STAMPS)
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vsim-regression-tests: $(VSIM_REGRESSION_TEST_STAMPS)
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vsim-torture: $(VSIM_TORTURE_STAMPS)
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FSIM_VERILOG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-verilog.stamp)
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FSIM_DEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-debug.stamp)
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FSIM_NDEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-ndebug.stamp)
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||||
FSIM_ASM_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-asm-tests.stamp)
|
||||
FSIM_BMARK_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-bmark-tests.stamp)
|
||||
FSIM_REGRESSION_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-regression-tests.stamp)
|
||||
FSIM_TORTURE_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-torture-$(TORTURE_CONFIG).stamp)
|
||||
|
||||
fsim-verilog: $(FSIM_VERILOG_STAMPS)
|
||||
fsim-debug: $(FSIM_DEBUG_STAMPS)
|
||||
fsim-ndebug: $(FSIM_NDEBUG_STAMPS)
|
||||
fsim-asm-tests: $(FSIM_ASM_TEST_STAMPS)
|
||||
fsim-bmark-tests: $(FSIM_BMARK_TEST_STAMPS)
|
||||
fsim-regression-tests: $(FSIM_REGRESSION_TEST_STAMPS)
|
||||
fsim-torture: $(FSIM_TORTURE_STAMPS)
|
||||
|
||||
submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore $(ROCKETCHIP_ADDONS)
|
||||
|
||||
# Checks out all the rocket-chip submodules
|
||||
@ -159,21 +142,6 @@ stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
|
||||
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug
|
||||
date > $@
|
||||
|
||||
stamps/%/fsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
|
||||
mkdir -p $(dir $@)
|
||||
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog
|
||||
date > $@
|
||||
|
||||
stamps/%/fsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
|
||||
mkdir -p $(dir $@)
|
||||
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION)
|
||||
date > $@
|
||||
|
||||
stamps/%/fsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
|
||||
mkdir -p $(dir $@)
|
||||
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug
|
||||
date > $@
|
||||
|
||||
# Runs tests on one of the simulators
|
||||
stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
|
||||
mkdir -p $(dir $@)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user