riscv/rocket-chip
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Remove fsim, as it is the same as vsim, modulo CONFIG

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Andrew Waterman committed 2016-08-09 15:42:22 -07:00
1 parent 1b8f919db2
commit 2906c75167
7 files changed
+12 -375
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.travis.yml
-1
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@@ -47,7 +47,6 @@ before_install:
script:
- make vsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
- make fsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
- make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
- make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION