riscv/rocket-chip
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clint/plic: Move the default addresses

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Megan Wachs committed 2016-10-01 15:46:55 -07:00
1 parent 9a381e88d1
commit 28eba9b5ac
2 files changed
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src/main/scala/uncore/devices/Prci.scala
+1 -1
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@@ -19,7 +19,7 @@ class CoreplexLocalInterrupts extends Bundle {
val msip = Bool()
}
case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x44000000) {
case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x02000000) {
def msipOffset(hart: Int) = hart * msipBytes
def msipAddress(hart: Int) = address + msipOffset(hart)
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes