riscv/rocket-chip
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Make any intervening load/store/fence fail an LR/SC sequence

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This catches LR/SC misuses more quickly.
This commit is contained in:
Andrew Waterman 2016-10-03 17:44:31 -07:00
parent 23c8b06d4a
commit 28beb33943
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/rocket/dcache.scala
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@ -197,7 +197,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
lrscAddr := s2_req.addr >> blockOffBits
}
when (lrscValid) { lrscCount := lrscCount - 1 }
when ((s2_valid_hit && s2_sc) || io.cpu.invalidate_lr) { lrscCount := 0 }
when ((s2_valid_masked && lrscValid) || io.cpu.invalidate_lr) { lrscCount := 0 }
// pending store buffer
val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)

4
src/main/scala/rocket/nbdcache.scala
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@ -926,10 +926,10 @@ class HellaCache(cfg: DCacheConfig)(implicit p: Parameters) extends L1HellaCache
when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
when (s2_valid_masked && s2_hit || s2_replay) {
when (s2_lr) {
when (!lrsc_valid) { lrsc_count := lrscCycles-1 }
lrsc_count := lrscCycles - 1
lrsc_addr := s2_req.addr >> blockOffBits
}
when (s2_sc) {
when (lrsc_valid) {
lrsc_count := 0
}
}