From 287bc1c2625f236002b7a20b51d56bcedd3eef54 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 13 Mar 2012 11:48:12 -0700 Subject: [PATCH] Further refinement of tag_match/tag_hit signals --- rocket/src/main/scala/nbdcache.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 3e38b505..f0058175 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -776,11 +776,11 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb) val tag_match_arr = (0 until NWAYS).map( w => isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_match = Cat(Bits(0),tag_match_arr:_*).orR - val hit_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec + val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec val tag_hit_arr = (0 until NWAYS).map( w => isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) - val tag_hit = Cat(Bits(0),tag_match_arr:_*).orR - val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), hit_way_oh, meta.io.way_en) - val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), hit_way_oh, data.io.way_en) + val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR + val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en) + val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en) val meta_resp_mux = Mux1H(meta_resp_way_oh, meta.io.resp) val data_resp_mux = Mux1H(data_resp_way_oh, data.io.resp) @@ -838,7 +838,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { meta.io.state_req.bits.inner_req.rw := Bool(true) meta.io.state_req.bits.inner_req.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb)) meta.io.state_req.bits.inner_req.data.state := Reg(new_hit_state) - meta.io.state_req.bits.way_en := Reg(hit_way_oh) + meta.io.state_req.bits.way_en := Reg(tag_match_way_oh) meta.io.state_req.valid := Reg(set_hit_state, resetVal = Bool(false)) // pending store data, also used for AMO RHS @@ -847,7 +847,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { p_store_idx := r_cpu_req_idx p_store_type := r_cpu_req_type p_store_cmd := r_cpu_req_cmd - p_store_way_oh := Mux(r_replay_amo, r_way_oh, hit_way_oh) + p_store_way_oh := Mux(r_replay_amo, r_way_oh, tag_match_way_oh) p_store_data := cpu_req_data } when (p_amo) { @@ -865,7 +865,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { mshr.io.req.bits.offset := r_cpu_req_idx(offsetmsb,0) mshr.io.req.bits.cmd := r_cpu_req_cmd mshr.io.req.bits.typ := r_cpu_req_type - mshr.io.req.bits.way_oh := Mux(tag_match, hit_way_oh, replaced_way_oh) + mshr.io.req.bits.way_oh := Mux(tag_match, tag_match_way_oh, replaced_way_oh) mshr.io.req.bits.data := cpu_req_data mshr.io.mem_rep <> io.mem.xact_rep