Merge pull request #851 from freechipsproject/chisel3clock

Use chisel3 Clock() method.

src/main/scala/jtag/JtagTap.scala

@@ -8,7 +8,7 @@ import chisel3.util._
   */
 class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
   val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
-  val TCK   = Clock(OUTPUT)
+  val TCK   = Output(Clock())
   val TMS   = Output(Bool())
   val TDI   = Output(Bool())
   val TDO   = Input(new Tristate())