Merge pull request #851 from freechipsproject/chisel3clock
Use chisel3 Clock() method.
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287219da06
@ -8,7 +8,7 @@ import chisel3.util._
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*/
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class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
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val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
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val TCK = Clock(OUTPUT)
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val TCK = Output(Clock())
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val TMS = Output(Bool())
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val TDI = Output(Bool())
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val TDO = Input(new Tristate())
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