riscv/rocket-chip
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New Mux1H constructor

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This commit is contained in:
Henry Cook
2012-02-01 13:24:28 -08:00
parent 38c9105ea1
commit 281abfbccb
2 changed files with 52 additions and 9 deletions
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6
rocket/src/main/scala/nbdcache.scala
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@ -289,9 +289,9 @@ class MSHRFile extends Component {
val replay = (new ioDecoupled) { new Replay() }.flip()
}
val tag_mux = new Mux1H(NMSHR, PPN_BITS)
val mem_resp_idx_mux = new Mux1H(NMSHR, IDX_BITS)
val mem_resp_way_id_mux = new Mux1H(NMSHR, log2up(NWAYS))
val tag_mux = (new Mux1H(NMSHR)){ Bits(width = PPN_BITS) }
val mem_resp_idx_mux = (new Mux1H(NMSHR)){ Bits(width = IDX_BITS) }
val mem_resp_way_oh_mux = (new Mux1H(NMSHR)){ Bits(width = NWAYS) }
val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayArrayReq() }
val mem_req_arb = (new Arbiter(NMSHR)) { new MemReq() }
val replay_arb = (new Arbiter(NMSHR)) { new Replay() }