nearly all isa tests pass
This commit is contained in:
Henry Cook
parent
a891ba1d46
commit
27c72e5eed
@ -157,13 +157,13 @@ class L2MetadataArray extends L2HellaCacheModule {
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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//val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val replacer = params(Replacer)()
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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when(!s2_tag_match) { replacer.miss }
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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@ -197,9 +197,9 @@ class L2DataArray extends L2HellaCacheModule {
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(wordBits, io.write.bits.wmask)
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val wmask = FillInterleaved(8, io.write.bits.wmask)
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val resp = (0 until nWays).map { w =>
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val array = Mem(Bits(width=params(RowBits)), nSets*refillCycles, seqRead = true)
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val array = Mem(Bits(width=rowBits), nSets*refillCycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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@ -258,7 +258,7 @@ class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCac
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def doInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o, i) => o.valid := UInt(i) === in.bits.id }
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outs.zipWithIndex.map { case (o, i) => o.valid := in.valid && (UInt(i) === in.bits.id) }
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}
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// Create TSHRs for outstanding transactions
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@ -295,8 +295,7 @@ class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCac
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
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val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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@ -361,7 +360,7 @@ abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCa
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}
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class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
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val s_idle :: s_meta_read :: s_meta_resp :: s_meta_write :: s_data_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 7)
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val s_idle :: s_meta_read :: s_meta_resp :: s_data_write :: s_meta_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 7)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Release }
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val xact_internal = Reg{ new L2MetaResp }
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@ -373,11 +372,12 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.finish.ready := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := init_client_id
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io.inner.grant.bits.payload := Grant(co.getGrantType(xact, xact_internal.meta.coh),
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@ -399,7 +399,10 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
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io.meta_write.bits.id := UInt(trackerId)
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io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
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io.meta_write.bits.way_en := xact_internal.way_en
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io.meta_write.bits.data := xact_internal.meta
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io.meta_write.bits.data.tag := xact.addr >> UInt(untagBits)
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io.meta_write.bits.data.coh := co.masterMetadataOnRelease(xact,
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xact_internal.meta.coh,
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init_client_id)
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switch (state) {
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is(s_idle) {
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@ -416,9 +419,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
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}
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is(s_meta_resp) {
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when(io.meta_resp.valid) {
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xact_internal := co.masterMetadataOnRelease(xact,
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io.meta_resp.bits.meta.coh,
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init_client_id)
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xact_internal := io.meta_resp.bits
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state := Mux(io.meta_resp.bits.tag_match,
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Mux(co.messageHasData(xact), s_data_write, s_meta_write),
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s_grant)
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@ -440,6 +441,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
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}
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}
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is(s_busy) {
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io.inner.finish.ready := Bool(true)
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when(io.inner.finish.valid) { state := s_idle }
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}
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}
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@ -450,15 +452,28 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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val state = Reg(init=s_idle)
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val xact = Reg{ new Acquire }
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val xact_internal = Reg{ new L2MetaResp }
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val test = Reg{UInt()}
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val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
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//TODO: Will need id reg for merged release xacts
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val init_client_id = Reg(init = UInt(0, width = log2Up(nClients)))
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val crel_had_data = Reg(init = Bool(false))
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val crel_was_voluntary = Reg(init = Bool(false))
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val crel_wb_src = Reg(init = UInt(0, width = log2Up(nClients)))
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val crel_wb_g_type = Reg(init = UInt(0, width = co.grantTypeWidth))
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val wb_buffer = Reg{xact.data.clone}
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val release_count = Reg(init = UInt(0, width = log2Up(nClients)))
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val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
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val pending_probes = Reg(init = co.dir().flush)
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val curr_p_id = co.dir().next(pending_probes)
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val is_uncached = co.messageIsUncached(xact)
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val tag_match = xact_internal.tag_match
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val needs_writeback = !tag_match && co.needsWriteback(xact_internal.meta.coh)
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val is_hit = tag_match && co.isHit(xact, xact_internal.meta.coh)
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val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh)
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//TODO: does allocate
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
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(state != s_idle) //TODO: Also indexes
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
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(state != s_idle) //TODO: Also indexes?
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val next_coh_on_release = co.masterMetadataOnRelease(
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c_rel.payload,
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@ -468,29 +483,14 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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c_gnt.payload,
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xact_internal.meta.coh,
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c_gnt.header.dst)
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val is_uncached = co.messageIsUncached(xact)
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val tag_match = xact_internal.tag_match
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val needs_writeback = co.needsWriteback(xact_internal.meta.coh)
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val is_hit = co.isHit(xact, xact_internal.meta.coh)
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val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh)
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//TODO: does allocate
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val c_rel_had_data = Reg(init = Bool(false))
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val c_rel_was_voluntary = Reg(init = Bool(false))
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val wb_buffer = Reg{xact.data.clone}
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
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(state != s_idle) //TODO: Also indexes
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
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(state != s_idle) //TODO: Also indexes?
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val addr_wb = Cat(xact_internal.meta.tag, xact.addr(untagBits-1,blockOffBits))
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val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType,
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xact.addr,
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UInt(trackerId),
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xact.data), { case TLId => outerId })
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val outer_write_wb = Bundle(Acquire(co.getUncachedWriteAcquireType,
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Cat(xact_internal.meta.tag,
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xact.addr(untagBits-1,blockOffBits)),
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addr_wb,
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UInt(trackerId),
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wb_buffer), { case TLId => outerId })
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val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType,
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@ -501,31 +501,33 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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io.outer.acquire.bits.header.src := UInt(bankId)
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io.outer.grant.ready := Bool(true) //grant.data -> xact.data
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val inner_probe_cacq = Probe(co.getProbeType(xact, xact_internal.meta.coh),
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val cprb_for_cacq = Probe(co.getProbeType(xact, xact_internal.meta.coh),
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xact.addr,
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UInt(trackerId))
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val inner_probe_wb = Probe(co.getProbeTypeOnVoluntaryWriteback,
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xact.addr,
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val cprb_for_mwb = Probe(co.getProbeTypeOnVoluntaryWriteback,
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addr_wb,
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UInt(trackerId))
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//TODO inner_probe_mprb
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io.inner.probe.valid := Bool(false)
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io.inner.probe.bits.header.src := UInt(bankId)
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io.inner.probe.bits.header.dst := curr_p_id
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io.inner.probe.bits.payload := Mux(needs_writeback,
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inner_probe_wb,
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inner_probe_cacq)
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io.inner.probe.bits.payload := Mux(!tag_match && needs_writeback,
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cprb_for_mwb,
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cprb_for_cacq)
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val grant_type = co.getGrantType(xact, xact_internal.meta.coh)
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := init_client_id
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io.inner.grant.bits.payload := Grant(grant_type,
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val cgnt_for_cacq = Grant(co.getGrantType(xact, xact_internal.meta.coh),
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xact.client_xact_id,
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UInt(trackerId),
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xact.data)
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val cgnt_for_cwb = Grant(crel_wb_g_type, UInt(0), UInt(trackerId), UInt(0))
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := Mux(crel_was_voluntary, crel_wb_src, init_client_id)
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io.inner.grant.bits.payload := Mux(crel_was_voluntary, cgnt_for_cwb, cgnt_for_cacq)
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io.inner.acquire.ready := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.finish.ready := Bool(false)
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io.data_read.valid := Bool(false)
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io.data_read.bits.id := UInt(trackerId)
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@ -565,15 +567,18 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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when(io.meta_resp.valid) {
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val coh = io.meta_resp.bits.meta.coh
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val _tag_match = io.meta_resp.bits.tag_match
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val _needs_writeback = co.needsWriteback(coh)
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val _is_hit = co.isHit(xact, coh)
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val _needs_writeback = !_tag_match && co.needsWriteback(coh)
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val _is_hit = _tag_match && co.isHit(xact, coh)
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val _needs_probes = co.requiresProbes(xact.a_type, coh)
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xact_internal := io.meta_resp.bits
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when(_needs_probes) {
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pending_probes := coh.sharers
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release_count := co.dir().count(coh.sharers)
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c_rel_had_data := Bool(false)
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c_rel_was_voluntary := Bool(false)
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val mask_incoherent = co.dir().full(coh.sharers) & ~io.tile_incoherent
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val mask_self = mask_incoherent &
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~(!(co.requiresSelfProbe(xact.a_type) || _needs_writeback) << init_client_id)
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pending_probes := mask_self
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release_count := co.dir().count(mask_self)
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crel_had_data := Bool(false)
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crel_was_voluntary := Bool(false)
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}
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state := Mux(_tag_match,
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Mux(_is_hit,
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@ -585,21 +590,17 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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}
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}
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is(s_probe) {
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val skip = io.tile_incoherent(curr_p_id) ||
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((curr_p_id === init_client_id) &&
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!co.requiresSelfProbe(xact.a_type))
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io.inner.probe.valid := !(co.dir().none(pending_probes) || skip)
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when(io.inner.probe.ready || skip) {
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co.dir().pop(pending_probes, curr_p_id)
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io.inner.probe.valid := !co.dir().none(pending_probes)
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when(io.inner.probe.ready) {
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pending_probes := co.dir().pop(pending_probes, curr_p_id)
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}
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when(skip) { release_count := release_count - UInt(1) }
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// Handle releases, which may have data being written back
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io.inner.release.ready := Bool(true)
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when(io.inner.release.valid) {
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xact_internal.meta.coh := next_coh_on_release
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when(co.messageHasData(c_rel.payload)) {
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c_rel_had_data := Bool(true)
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crel_had_data := Bool(true)
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when(tag_match) {
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xact.data := mergeData(xact, io.inner.release.bits.payload.data)
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} .otherwise {
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@ -607,18 +608,28 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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}
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}
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when(co.isVoluntary(c_rel.payload)) {
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c_rel_was_voluntary := Bool(true)
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crel_was_voluntary := Bool(true)
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crel_wb_src := c_rel.header.src
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crel_wb_g_type := co.getGrantType(c_rel.payload, xact_internal.meta.coh)
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}
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when(!co.isVoluntary(c_rel.payload)) {
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release_count := release_count - Mux(skip, UInt(2), UInt(1))
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when(release_count === UInt(1)) {
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release_count := release_count - UInt(1)
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}
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}
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when(crel_was_voluntary) {
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io.inner.grant.valid := Bool(true)
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when(io.inner.grant.ready) {
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crel_was_voluntary := Bool(false)
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}
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}
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when(release_count === UInt(0) && !crel_was_voluntary) {
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state := Mux(tag_match,
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Mux(is_hit,
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Mux(c_rel_had_data, s_meta_write, s_data_read_hit),
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Mux(crel_had_data, s_data_write, s_data_read_hit),
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s_outer_read),
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Mux(c_rel_had_data, s_outer_write_wb, s_data_read_wb))
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}
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}
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Mux(crel_had_data, s_outer_write_wb, s_data_read_wb))
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}
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}
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is(s_data_read_wb) {
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@ -686,6 +697,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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}
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}
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is(s_busy) {
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io.inner.finish.ready := Bool(true)
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when(io.inner.finish.valid) { state := s_idle }
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}
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}
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@ -58,6 +58,7 @@ abstract class DirectoryRepresentation(val width: Int) {
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def one(s: UInt): Bool
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def count(s: UInt): UInt
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def next(s: UInt): UInt
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def full(s: UInt): UInt
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}
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class NullRepresentation extends DirectoryRepresentation(1) {
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@ -68,6 +69,7 @@ class NullRepresentation extends DirectoryRepresentation(1) {
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def one(s: UInt) = Bool(false)
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def count(s: UInt) = UInt(0)
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def next(s: UInt) = UInt(0)
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def full(s: UInt) = UInt(0)
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}
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class FullRepresentation(nClients: Int) extends DirectoryRepresentation(nClients) {
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@ -78,6 +80,7 @@ class FullRepresentation(nClients: Int) extends DirectoryRepresentation(nClients
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def one(s: UInt) = PopCount(s) === UInt(1)
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def count(s: UInt) = PopCount(s)
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def next(s: UInt) = PriorityEncoder(s)
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def full(s: UInt) = s
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}
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abstract class CoherencePolicy(val dir: () => DirectoryRepresentation) {
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@ -147,6 +150,7 @@ trait UncachedTransactions {
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def getUncachedWriteWordAcquireType: UInt
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def getUncachedAtomicAcquireType: UInt
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def isUncachedReadTransaction(acq: Acquire): Bool
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def getUncachedReadGrantType: UInt
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}
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abstract class CoherencePolicyWithUncached(dir: () => DirectoryRepresentation) extends CoherencePolicy(dir)
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@ -234,6 +238,8 @@ class MICoherence(dir: () => DirectoryRepresentation) extends CoherencePolicyWit
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def getUncachedWriteWordAcquireType = acquireWriteWordUncached
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||||
def getUncachedAtomicAcquireType = acquireAtomicUncached
|
||||
def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached
|
||||
def getUncachedReadGrantType = grantReadUncached
|
||||
|
||||
def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData
|
||||
def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
|
||||
|
||||
@ -399,6 +405,8 @@ class MEICoherence(dir: () => DirectoryRepresentation) extends CoherencePolicyWi
|
||||
def getUncachedWriteWordAcquireType = acquireWriteWordUncached
|
||||
def getUncachedAtomicAcquireType = acquireAtomicUncached
|
||||
def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached
|
||||
def getUncachedReadGrantType = grantReadUncached
|
||||
|
||||
def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData
|
||||
def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
|
||||
|
||||
@ -579,6 +587,8 @@ class MSICoherence(dir: () => DirectoryRepresentation) extends CoherencePolicyWi
|
||||
def getUncachedWriteWordAcquireType = acquireWriteWordUncached
|
||||
def getUncachedAtomicAcquireType = acquireAtomicUncached
|
||||
def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached
|
||||
def getUncachedReadGrantType = grantReadUncached
|
||||
|
||||
def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData
|
||||
def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
|
||||
|
||||
@ -756,6 +766,8 @@ class MESICoherence(dir: () => DirectoryRepresentation) extends CoherencePolicyW
|
||||
def getUncachedWriteWordAcquireType = acquireWriteWordUncached
|
||||
def getUncachedAtomicAcquireType = acquireAtomicUncached
|
||||
def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached
|
||||
def getUncachedReadGrantType = grantReadUncached
|
||||
|
||||
def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData
|
||||
def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
|
||||
|
||||
@ -954,6 +966,8 @@ class MigratoryCoherence(dir: () => DirectoryRepresentation) extends CoherencePo
|
||||
def getUncachedWriteWordAcquireType = acquireWriteWordUncached
|
||||
def getUncachedAtomicAcquireType = acquireAtomicUncached
|
||||
def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached
|
||||
def getUncachedReadGrantType = grantReadUncached
|
||||
|
||||
def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData
|
||||
def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
|
||||
|
||||
|
||||
@ -268,7 +268,7 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int) extends Module {
|
||||
// Aggregate incoming MemIO responses into TL Grants
|
||||
io.mem.resp.ready := !active_in || cnt_in < UInt(cnt_max)
|
||||
io.uncached.grant.valid := active_in && (cnt_in === UInt(cnt_max))
|
||||
io.uncached.grant.bits.payload := Grant(UInt(0), tag_in, UInt(0), buf_in)
|
||||
io.uncached.grant.bits.payload := Grant(co.getUncachedReadGrantType, tag_in, UInt(0), buf_in)
|
||||
when(!active_in && io.mem.resp.valid) {
|
||||
active_in := Bool(true)
|
||||
cnt_in := UInt(1)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user