riscv/rocket-chip
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new tilelink arbiter types, reduced release xact trackers

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This commit is contained in:
Henry Cook
2013-07-09 15:41:27 -07:00
parent c5f01f3f87
commit 2796de01bf
6 changed files with 6 additions and 6 deletions
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2
src/main/scala/RocketChip.scala
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@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {

2
src/main/scala/fpga.scala
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@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {