riscv/rocket-chip
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tilelink2: define is{Request,Response} based on spec

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This commit is contained in:
Wesley W. Terpstra 2017-03-20 13:27:24 -07:00
parent 778e189bba
commit 278f6fea24
3 changed files with 15 additions and 3 deletions
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2
src/main/scala/rocket/DCache.scala
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@ -345,7 +345,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
// Finish TileLink transaction by issuing a GrantAck
grantackq.io.enq.valid := d_done && edge.hasFollowUp(tl_out.d.bits)
grantackq.io.enq.valid := d_done && edge.isRequest(tl_out.d.bits)
grantackq.io.enq.bits := edge.GrantAck(tl_out.d.bits)
tl_out.e <> grantackq.io.deq
assert(!grantackq.io.enq.valid || grantackq.io.enq.ready, "Too many Grants received by dcache.")

2
src/main/scala/rocket/NBDcache.scala
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@ -246,7 +246,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
val grantackq = Module(new Queue(io.mem_finish.bits, 1))
val can_finish = state.isOneOf(s_invalid, s_refill_req)
grantackq.io.enq.valid := refill_done && edge.hasFollowUp(io.mem_grant.bits)
grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits)
grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits)
io.mem_finish.valid := grantackq.io.deq.valid && can_finish
io.mem_finish.bits := grantackq.io.deq.bits

14
src/main/scala/uncore/tilelink2/Edges.scala
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@ -57,7 +57,7 @@ class TLEdge(
}
}
def hasFollowUp(x: TLChannel): Bool = {
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => Bool(true)
case b: TLBundleB => Bool(true)
@ -71,6 +71,18 @@ class TLEdge(
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => Bool(false)
case b: TLBundleB => Bool(false)
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => Bool(true) // Grant isResponse + isRequest
case e: TLBundleE => Bool(true)
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)