riscv/rocket-chip
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Give D$ RAMs consistent names

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Andrew Waterman
2017-03-30 15:44:34 -07:00
parent 70e7e90c02
commit 2720095b8e
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/DCache.scala
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@@ -26,9 +26,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val resp = Vec(nWays, Bits(OUTPUT, rowBits)) val resp = Vec(nWays, Bits(OUTPUT, rowBits))
} }
val data_arrays = Seq.fill(nWays) { SeqMem(nSets*refillCycles, Vec(rowBytes, Bits(width=8))) }
val addr = io.req.bits.addr >> rowOffBits val addr = io.req.bits.addr >> rowOffBits
for (w <- 0 until nWays) { for ((array, w) <- data_arrays zipWithIndex) {
val array = SeqMem(nSets*refillCycles, Vec(rowBytes, Bits(width=8)))
val valid = io.req.valid && (Bool(nWays == 1) || io.req.bits.way_en(w)) val valid = io.req.valid && (Bool(nWays == 1) || io.req.bits.way_en(w))
when (valid && io.req.bits.write) { when (valid && io.req.bits.write) {
val data = Vec.tabulate(rowBytes)(i => io.req.bits.wdata(8*(i+1)-1, 8*i)) val data = Vec.tabulate(rowBytes)(i => io.req.bits.wdata(8*(i+1)-1, 8*i))