From 26f9e2dfbd68a2503624b7915b594f4d0ae01307 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 10 Sep 2016 01:22:12 -0700 Subject: [PATCH] tilelink2 Parameters: fix width=1 address truncation bug --- src/main/scala/uncore/tilelink2/Parameters.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 82e0500a..4bda7612 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -322,7 +322,7 @@ case class TLEdgeParameters( require (maxTransfer >= manager.beatBytes) val bundle = TLBundleParameters( - addrHiBits = log2Up(manager.maxAddress + 1) - log2Up(manager.beatBytes), + addrHiBits = log2Up(manager.maxAddress + 1) - log2Ceil(manager.beatBytes), dataBits = manager.beatBytes * 8, sourceBits = log2Up(client.endSourceId), sinkBits = log2Up(manager.endSinkId),