riscv/rocket-chip
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tile: turn off more slave port monitors

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This commit is contained in:
Henry Cook 2017-07-27 15:28:53 -07:00
parent 9a483af6e8
commit 266ed56e8d
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/tile/RocketTile.scala
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@ -193,7 +193,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
masterNode :=* rocket.masterNode masterNode :=* rocket.masterNode
val slaveNode = new TLInputNode() { override def reverse = true } val slaveNode = new TLInputNode() { override def reverse = true }
rocket.slaveNode :*= slaveNode rocket.slaveNode connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers. // Fully async interrupts need synchronizers.
// Others need no synchronization. // Others need no synchronization.
@ -213,8 +213,8 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
val slaveNode = new TLAsyncInputNode() { override def reverse = true } val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink) val sink = LazyModule(new TLAsyncCrossingSink)
rocket.slaveNode :*= sink.node rocket.slaveNode connectButDontMonitorSlaves sink.node
sink.node :*= slaveNode sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers, // Fully async interrupts need synchronizers,
// as do those coming from the periphery clock. // as do those coming from the periphery clock.
@ -237,8 +237,8 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
val slaveNode = new TLRationalInputNode() { override def reverse = true } val slaveNode = new TLRationalInputNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast)) val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
rocket.slaveNode :*= sink.node rocket.slaveNode connectButDontMonitorSlaves sink.node
sink.node :*= slaveNode sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers. // Fully async interrupts need synchronizers.
// Those coming from periphery clock need a // Those coming from periphery clock need a